JPS5555548A - Method of fabricating semiconductor device - Google Patents

Method of fabricating semiconductor device

Info

Publication number
JPS5555548A
JPS5555548A JP12835078A JP12835078A JPS5555548A JP S5555548 A JPS5555548 A JP S5555548A JP 12835078 A JP12835078 A JP 12835078A JP 12835078 A JP12835078 A JP 12835078A JP S5555548 A JPS5555548 A JP S5555548A
Authority
JP
Japan
Prior art keywords
film
semiconductor device
psg film
heat resistant
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12835078A
Other languages
Japanese (ja)
Inventor
Tatsumi Shirasu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12835078A priority Critical patent/JPS5555548A/en
Publication of JPS5555548A publication Critical patent/JPS5555548A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: To provide a stable passivation film on a semiconductor device by forming a wiring layer by heat resistant conductor and densifying it at higher than 600°C after forming a PSG film.
CONSTITUTION: A field SiO2 film 3 is formed on an N-type silicon semiconductor substrate 1, and source and drain 2 are formed thereon by photoetching process. Then, a high heat resistant matal layer 9 is formed thereon by deposition or spattering, partially removed thereat, and executed by phosphorus dope silane deposition to thereby form a PSG film 10 thereon. Then, it is annealed by N2 at 600°W1000°C., and the PSG film is densified, and a bump electrode 11 is then formed thereon.
COPYRIGHT: (C)1980,JPO&Japio
JP12835078A 1978-10-20 1978-10-20 Method of fabricating semiconductor device Pending JPS5555548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12835078A JPS5555548A (en) 1978-10-20 1978-10-20 Method of fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12835078A JPS5555548A (en) 1978-10-20 1978-10-20 Method of fabricating semiconductor device

Publications (1)

Publication Number Publication Date
JPS5555548A true JPS5555548A (en) 1980-04-23

Family

ID=14982630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12835078A Pending JPS5555548A (en) 1978-10-20 1978-10-20 Method of fabricating semiconductor device

Country Status (1)

Country Link
JP (1) JPS5555548A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6386549A (en) * 1986-09-30 1988-04-16 Toshiba Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6386549A (en) * 1986-09-30 1988-04-16 Toshiba Corp Manufacture of semiconductor device

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