JPS54162463A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS54162463A
JPS54162463A JP7170878A JP7170878A JPS54162463A JP S54162463 A JPS54162463 A JP S54162463A JP 7170878 A JP7170878 A JP 7170878A JP 7170878 A JP7170878 A JP 7170878A JP S54162463 A JPS54162463 A JP S54162463A
Authority
JP
Japan
Prior art keywords
film
flat
mask
layer
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7170878A
Other languages
Japanese (ja)
Inventor
Hiroyasu Karimoto
Kosei Kajiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7170878A priority Critical patent/JPS54162463A/en
Publication of JPS54162463A publication Critical patent/JPS54162463A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Abstract

PURPOSE: To prevent the occurrence of cracks for the insulating film, by making flat the surface of the bump metal welded to the leads and making uniform the stress with broader contact area.
CONSTITUTION: The Al wiring 53 is formed on the SiO2 film 52 of the Si substrate 51, the SiO2 54 is etched and opened 56 with the resist mask 55 and the Al layer 57 having the same thickness as the film 54 is evaporated. The mask 55 is removed and the double layered film 59 of Cr-Cu is evaporated on the flat surface in which the Al layer 58 is incorporated. When the Au bump electrode 61 is made with the resist mask 60 having greater window than the layer 58 by taking the film 59 as the plating electrode, since no step difference at the window open part is present, the bump top surface is flat. The resist 60 is removed, the film 59 is etched with the resist mask 62, the mask 62 is made flat to produce chips. Further, the bump metal 61 and the leads on the film carrier are thermally pressed. At this time, the stress is exerted uniformly on the surface of the electrode 61, it is buffered with the layers 58 and 53, and the reliability of the device can greatly be increased without damaging the insulation film.
COPYRIGHT: (C)1979,JPO&Japio
JP7170878A 1978-06-13 1978-06-13 Semiconductor device and its manufacture Pending JPS54162463A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7170878A JPS54162463A (en) 1978-06-13 1978-06-13 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7170878A JPS54162463A (en) 1978-06-13 1978-06-13 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS54162463A true JPS54162463A (en) 1979-12-24

Family

ID=13468299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7170878A Pending JPS54162463A (en) 1978-06-13 1978-06-13 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS54162463A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0551723U (en) * 1991-12-11 1993-07-09 凸版印刷株式会社 Blank board for bag-in-box outer box

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52155054A (en) * 1976-06-18 1977-12-23 Matsushita Electric Ind Co Ltd Production of semiconductor device
JPS5343474A (en) * 1976-10-01 1978-04-19 Seiko Epson Corp Semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52155054A (en) * 1976-06-18 1977-12-23 Matsushita Electric Ind Co Ltd Production of semiconductor device
JPS5343474A (en) * 1976-10-01 1978-04-19 Seiko Epson Corp Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0551723U (en) * 1991-12-11 1993-07-09 凸版印刷株式会社 Blank board for bag-in-box outer box

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