JPS5343474A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS5343474A
JPS5343474A JP11825976A JP11825976A JPS5343474A JP S5343474 A JPS5343474 A JP S5343474A JP 11825976 A JP11825976 A JP 11825976A JP 11825976 A JP11825976 A JP 11825976A JP S5343474 A JPS5343474 A JP S5343474A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
bonding
making
reliability
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11825976A
Other languages
Japanese (ja)
Inventor
Takeo Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP11825976A priority Critical patent/JPS5343474A/en
Publication of JPS5343474A publication Critical patent/JPS5343474A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To improve the reliability of bonding by making the central part of a bump electrode convex as compared to the outside circumferential part of the surface thereof thereby making positive the contact at the bonding with an external lead terminal.
COPYRIGHT: (C)1978,JPO&Japio
JP11825976A 1976-10-01 1976-10-01 Semiconductor integrated circuit Pending JPS5343474A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11825976A JPS5343474A (en) 1976-10-01 1976-10-01 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11825976A JPS5343474A (en) 1976-10-01 1976-10-01 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5343474A true JPS5343474A (en) 1978-04-19

Family

ID=14732183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11825976A Pending JPS5343474A (en) 1976-10-01 1976-10-01 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5343474A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54162463A (en) * 1978-06-13 1979-12-24 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54162463A (en) * 1978-06-13 1979-12-24 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacture

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