JPS5354469A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS5354469A
JPS5354469A JP12976876A JP12976876A JPS5354469A JP S5354469 A JPS5354469 A JP S5354469A JP 12976876 A JP12976876 A JP 12976876A JP 12976876 A JP12976876 A JP 12976876A JP S5354469 A JPS5354469 A JP S5354469A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
bonding
shape
undulations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12976876A
Other languages
Japanese (ja)
Inventor
Takeo Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP12976876A priority Critical patent/JPS5354469A/en
Publication of JPS5354469A publication Critical patent/JPS5354469A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To increase the contact area with fingers at the bonding and enhance the reliability of bonding by forming the top sectional shape of bump electrodes in an IC to a shape having a plurality of undulations.
COPYRIGHT: (C)1978,JPO&Japio
JP12976876A 1976-10-28 1976-10-28 Semiconductor integrated circuit Pending JPS5354469A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12976876A JPS5354469A (en) 1976-10-28 1976-10-28 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12976876A JPS5354469A (en) 1976-10-28 1976-10-28 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5354469A true JPS5354469A (en) 1978-05-17

Family

ID=15017716

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12976876A Pending JPS5354469A (en) 1976-10-28 1976-10-28 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5354469A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58175849A (en) * 1982-04-08 1983-10-15 Agency Of Ind Science & Technol Semiconductor device
JPH03242938A (en) * 1990-02-21 1991-10-29 Matsushita Electron Corp Semiconductor device
JPH06283536A (en) * 1993-03-30 1994-10-07 Nec Corp Solder bump packaging substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58175849A (en) * 1982-04-08 1983-10-15 Agency Of Ind Science & Technol Semiconductor device
JPH03242938A (en) * 1990-02-21 1991-10-29 Matsushita Electron Corp Semiconductor device
JPH06283536A (en) * 1993-03-30 1994-10-07 Nec Corp Solder bump packaging substrate

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