JPS5648165A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS5648165A
JPS5648165A JP12409879A JP12409879A JPS5648165A JP S5648165 A JPS5648165 A JP S5648165A JP 12409879 A JP12409879 A JP 12409879A JP 12409879 A JP12409879 A JP 12409879A JP S5648165 A JPS5648165 A JP S5648165A
Authority
JP
Japan
Prior art keywords
layer
polycrystalline silicon
high resistance
film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12409879A
Other languages
English (en)
Other versions
JPS6336140B2 (ja
Inventor
Akira Nagai
Akira Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12409879A priority Critical patent/JPS5648165A/ja
Publication of JPS5648165A publication Critical patent/JPS5648165A/ja
Publication of JPS6336140B2 publication Critical patent/JPS6336140B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP12409879A 1979-09-28 1979-09-28 Preparation of semiconductor device Granted JPS5648165A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12409879A JPS5648165A (en) 1979-09-28 1979-09-28 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12409879A JPS5648165A (en) 1979-09-28 1979-09-28 Preparation of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5648165A true JPS5648165A (en) 1981-05-01
JPS6336140B2 JPS6336140B2 (ja) 1988-07-19

Family

ID=14876865

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12409879A Granted JPS5648165A (en) 1979-09-28 1979-09-28 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5648165A (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59225565A (ja) * 1983-06-06 1984-12-18 Mitsubishi Electric Corp 半導体装置における金属バラスト抵抗の製造方法
JPS60116272A (ja) * 1983-11-28 1985-06-22 Fujitsu Ltd フアクシミリの送信制御方式
JPS61230363A (ja) * 1985-04-04 1986-10-14 Fujitsu Ten Ltd 半導体集積装置
JPS62154778A (ja) * 1985-12-20 1987-07-09 エス　ジ−　エス　ミクロ　エレトロニカ　エス．ピ−．エ−． モノリシック集積回路の製造方法
JPH01302748A (ja) * 1988-05-30 1989-12-06 Sharp Corp 半導体装置の製造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59225565A (ja) * 1983-06-06 1984-12-18 Mitsubishi Electric Corp 半導体装置における金属バラスト抵抗の製造方法
JPH0312459B2 (ja) * 1983-06-06 1991-02-20 Mitsubishi Electric Corp
JPS60116272A (ja) * 1983-11-28 1985-06-22 Fujitsu Ltd フアクシミリの送信制御方式
JPH0473341B2 (ja) * 1983-11-28 1992-11-20 Fujitsu Ltd
JPS61230363A (ja) * 1985-04-04 1986-10-14 Fujitsu Ten Ltd 半導体集積装置
JPS62154778A (ja) * 1985-12-20 1987-07-09 エス　ジ−　エス　ミクロ　エレトロニカ　エス．ピ−．エ−． モノリシック集積回路の製造方法
JPH01302748A (ja) * 1988-05-30 1989-12-06 Sharp Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
JPS6336140B2 (ja) 1988-07-19

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