JPS5683061A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5683061A
JPS5683061A JP16055979A JP16055979A JPS5683061A JP S5683061 A JPS5683061 A JP S5683061A JP 16055979 A JP16055979 A JP 16055979A JP 16055979 A JP16055979 A JP 16055979A JP S5683061 A JPS5683061 A JP S5683061A
Authority
JP
Japan
Prior art keywords
film
layer
polycrystal silicon
polycrystal
molybdenum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16055979A
Other languages
Japanese (ja)
Inventor
Keizo Kobayashi
Yukinobu Murao
Osamu Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16055979A priority Critical patent/JPS5683061A/en
Publication of JPS5683061A publication Critical patent/JPS5683061A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To form a resistor in a self-matching shape and obtain a semiconductor device having a high degree of integration by a method wherein impurities are selectively introduced into a polycrystal silicon layer forming a gate electrode, using high melting-point metal wiring layers made up on the polycrystal layer as masks. CONSTITUTION:An N type impurity diffusion layer 102 formed on a P type silicon substrate 101 and polycrystal silicon films 103, 104 are glued. A molybdenum film 105 is disposed through a layer silicon oxide film 108, and an aluminum film 106 is arranged through a layer film 109. Since the polycrystal silicon film 104 is coated with the molybdenum film 105, impurities are not introduced by the injection of arsenic ions for forming the N type region 102, and the polycrystal silicon film 104 is changed into a resistance element self-matched with the molybdenum wiring layer 105. The polycrystal silicon film 103 is turned into a wiring layer with low resistance because arsenic is sufficiently introduced.
JP16055979A 1979-12-11 1979-12-11 Semiconductor device Pending JPS5683061A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16055979A JPS5683061A (en) 1979-12-11 1979-12-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16055979A JPS5683061A (en) 1979-12-11 1979-12-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5683061A true JPS5683061A (en) 1981-07-07

Family

ID=15717599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16055979A Pending JPS5683061A (en) 1979-12-11 1979-12-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5683061A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745967A (en) * 1980-09-04 1982-03-16 Toshiba Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745967A (en) * 1980-09-04 1982-03-16 Toshiba Corp Semiconductor device

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