JPS5629342A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5629342A JPS5629342A JP10464279A JP10464279A JPS5629342A JP S5629342 A JPS5629342 A JP S5629342A JP 10464279 A JP10464279 A JP 10464279A JP 10464279 A JP10464279 A JP 10464279A JP S5629342 A JPS5629342 A JP S5629342A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- ions
- implanted
- yield
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76289—Lateral isolation by air gap
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To contrive the improvement in the shortening of steps of manufacturing a semiconductor device and the yield thereof by forming simultaneously an impurity diffusing mask at the time of forming monocrystalline or polycrystalline Si resistor with another wire or using a wire formed on the resistance layer. CONSTITUTION:An SiO2 film 2 is formed on an Si substrate 1 to form selectively polysilicon layers 4, 5 thereon. It is thermally oxidized to form an SiO2 film 6 thereon, B ions are implanted thereon, and is coated then with polysilicon layer 7. It is photoetched to form wiring tubes 8, 9 thereon. Then, P ions are implanted in high density to form wiring layer 5b and resistance layer 5a thereon. When the superimposition of the polysilicon layers 5, 9 is reduced, the layer 5a is diffused from both sides by the heat treatment after implanting ions to form a wiring layer. In this manner the degree of freedom of designing is increased. This configuration can omit the step of manufacturing mask to improve the yield thereof.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10464279A JPS5629342A (en) | 1979-08-17 | 1979-08-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10464279A JPS5629342A (en) | 1979-08-17 | 1979-08-17 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5629342A true JPS5629342A (en) | 1981-03-24 |
Family
ID=14386099
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10464279A Pending JPS5629342A (en) | 1979-08-17 | 1979-08-17 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5629342A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5821426A (en) * | 1981-07-30 | 1983-02-08 | Teijin Ltd | Polymer having joined cytotoxic substance and preparation thereof |
JPH0729090U (en) * | 1993-11-09 | 1995-06-02 | 和仁 大野 | Concrete sewage basin |
US5639688A (en) * | 1993-05-21 | 1997-06-17 | Harris Corporation | Method of making integrated circuit structure with narrow line widths |
JP2009192082A (en) * | 2008-02-16 | 2009-08-27 | Dr Ing Hcf Porsche Ag | Transmission casing for motor vehicle |
US10527152B2 (en) | 2013-11-08 | 2020-01-07 | Sew-Eurodrive Gmbh & Co. Kg | Gear unit having a housing with lubrication groove |
-
1979
- 1979-08-17 JP JP10464279A patent/JPS5629342A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5821426A (en) * | 1981-07-30 | 1983-02-08 | Teijin Ltd | Polymer having joined cytotoxic substance and preparation thereof |
JPH029563B2 (en) * | 1981-07-30 | 1990-03-02 | Teijin Ltd | |
US5639688A (en) * | 1993-05-21 | 1997-06-17 | Harris Corporation | Method of making integrated circuit structure with narrow line widths |
US5773891A (en) * | 1993-05-21 | 1998-06-30 | Harris Corporation | Integrated circuit method for and structure with narrow line widths |
JPH0729090U (en) * | 1993-11-09 | 1995-06-02 | 和仁 大野 | Concrete sewage basin |
JP2009192082A (en) * | 2008-02-16 | 2009-08-27 | Dr Ing Hcf Porsche Ag | Transmission casing for motor vehicle |
US10527152B2 (en) | 2013-11-08 | 2020-01-07 | Sew-Eurodrive Gmbh & Co. Kg | Gear unit having a housing with lubrication groove |
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