JPS6425476A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS6425476A
JPS6425476A JP18150587A JP18150587A JPS6425476A JP S6425476 A JPS6425476 A JP S6425476A JP 18150587 A JP18150587 A JP 18150587A JP 18150587 A JP18150587 A JP 18150587A JP S6425476 A JPS6425476 A JP S6425476A
Authority
JP
Japan
Prior art keywords
melting point
oxide film
high melting
metal silicide
point metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18150587A
Other languages
Japanese (ja)
Inventor
Shigeji Yoshii
Shozo Okada
Kazuhiko Tsuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP18150587A priority Critical patent/JPS6425476A/en
Publication of JPS6425476A publication Critical patent/JPS6425476A/en
Pending legal-status Critical Current

Links

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To reduce a wiring delay and to stabilize element characteristics by forming a polycide structure formed with a polycrystalline silicon having stable element characteristic or a thin high melting point metal silicide on the polycrystalline silicon only in the gate wiring of a transistor forming region. CONSTITUTION:A polycrystalline silicon 14 is formed on a gate oxide film 16, and high melting point metal silicide of Mo, Ti, W, Ta and the like is further formed thereon. Then, the step 13 of a selective oxide film and the high melting point metal silicide 15 except a transistor 19 are etched with a resist mask of a predetermined pattern to expose part of the silicon 14. After the resist mask is removed, an interlayer insulating film 17 is formed, and aluminum wirings 18 are formed. In the above forming steps, the impurity implantation into the silicon 14 is conducted by a POCl3 diffusing method or a phosphorus ion implanting method to obtain preferable characteristic of gate oxide film breakdown strength.
JP18150587A 1987-07-21 1987-07-21 Semiconductor device and manufacture thereof Pending JPS6425476A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18150587A JPS6425476A (en) 1987-07-21 1987-07-21 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18150587A JPS6425476A (en) 1987-07-21 1987-07-21 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS6425476A true JPS6425476A (en) 1989-01-27

Family

ID=16101934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18150587A Pending JPS6425476A (en) 1987-07-21 1987-07-21 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6425476A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5188962A (en) * 1990-10-09 1993-02-23 Eisai Co., Ltd. Cell cultivating apparatus
CN104257311A (en) * 2010-12-17 2015-01-07 科勒公司 Shower Bar System

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5188962A (en) * 1990-10-09 1993-02-23 Eisai Co., Ltd. Cell cultivating apparatus
CN104257311A (en) * 2010-12-17 2015-01-07 科勒公司 Shower Bar System

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