JPS56158471A - Manufacture of semiconductor storage device - Google Patents
Manufacture of semiconductor storage deviceInfo
- Publication number
- JPS56158471A JPS56158471A JP6428180A JP6428180A JPS56158471A JP S56158471 A JPS56158471 A JP S56158471A JP 6428180 A JP6428180 A JP 6428180A JP 6428180 A JP6428180 A JP 6428180A JP S56158471 A JPS56158471 A JP S56158471A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- bit line
- substrate
- section
- capacity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 3
- 238000000034 method Methods 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Semiconductor Memories (AREA)
Abstract
PURPOSE:To obtain the cell having the reduced influence of alpha rays as well as to enable to obtain a high speed operation for MOSRAM by a method wherein a bit line is formed using the polycrystalline Si of the conductive type reverse to a substrate, is arranged on a thick oxide film and a diffusing region is provided only at the section connected to the substrate. CONSTITUTION:The thick oxide film 2 is formed on a P type substrate 1, the oxide film 2 located at a capacity section and an FET section is removed and a thin oxide film 2a is formed. Then, an aperture is provided on the oxide film 2a located at the section (source and drain section) connecting to the bit line, the bit line consisting of an N<+> doped polycrystalline Si 6 is provided and an N<+> layer 8 is diffused on the substrate. Then, a capacity electrode 3 and a gate electrode 4 are formed using a double-layer polycrystalline Si structure and is used as a cell FET. Through these procedures, the area of N<+> region connected to the bit line is reduced, the carrier is hard to be collected by the alpha rays and the variation of the bit line electrode can be prevented. Also, because of the wiring performed on the thick oxide film, the capacity between the bit line and the substrate is reduced and a high speed operation can be performed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6428180A JPS56158471A (en) | 1980-05-12 | 1980-05-12 | Manufacture of semiconductor storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6428180A JPS56158471A (en) | 1980-05-12 | 1980-05-12 | Manufacture of semiconductor storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56158471A true JPS56158471A (en) | 1981-12-07 |
Family
ID=13253682
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6428180A Pending JPS56158471A (en) | 1980-05-12 | 1980-05-12 | Manufacture of semiconductor storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56158471A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3529199A1 (en) * | 1984-08-16 | 1986-02-27 | Nissan Motor Co., Ltd., Yokohama, Kanagawa | VIBRATION DAMPING SYSTEM |
-
1980
- 1980-05-12 JP JP6428180A patent/JPS56158471A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3529199A1 (en) * | 1984-08-16 | 1986-02-27 | Nissan Motor Co., Ltd., Yokohama, Kanagawa | VIBRATION DAMPING SYSTEM |
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