JPS56153729A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56153729A
JPS56153729A JP5751180A JP5751180A JPS56153729A JP S56153729 A JPS56153729 A JP S56153729A JP 5751180 A JP5751180 A JP 5751180A JP 5751180 A JP5751180 A JP 5751180A JP S56153729 A JPS56153729 A JP S56153729A
Authority
JP
Japan
Prior art keywords
film
layer
prescribed temperature
substrate
crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5751180A
Other languages
Japanese (ja)
Inventor
Kazunori Fukuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5751180A priority Critical patent/JPS56153729A/en
Publication of JPS56153729A publication Critical patent/JPS56153729A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon

Abstract

PURPOSE:To contrive to reduce defect in the crystal and to prevent the increase of the leakage current of the semiconductor device by a method wherein a polycrystalline silicon film is provided in a semiconductor substrate, and proper energy sufficient to enable defect to operate is applied using the film thereof as a trapping material. CONSTITUTION:An N<+> type epitaxial layer 2 is formed on the semiconductor substrate 1, and after it is oxidized by heating at the prescribed temperature to form an insulating film 3 on the layer 2, an opening part 4 is formed in the film 3 by the photoetching method. Polycrystalline silicon films 5 are made to grow vapor phase epitaxially on the both faces of the substrate 1 according to the thermal decomposition method of siane. Moreover an insulating film 6 being made to contain an impurity containing boron is provided on the film 5, and in succession boron is made to diffuse at the prescribed temperature in the substrate 1 up to the desired depth to form a P type diffusion layer 7. Then the film 6 is removed by etching, and after it is heated at the prescribed temperature, an electrode 8 is formed on a part of the film 5, a P-N junction 9 is formed between the layer 7 and the layer 2 to reduce defect in the crystal and to prevent the increase of the leakage current.
JP5751180A 1980-04-30 1980-04-30 Manufacture of semiconductor device Pending JPS56153729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5751180A JPS56153729A (en) 1980-04-30 1980-04-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5751180A JPS56153729A (en) 1980-04-30 1980-04-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56153729A true JPS56153729A (en) 1981-11-27

Family

ID=13057753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5751180A Pending JPS56153729A (en) 1980-04-30 1980-04-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56153729A (en)

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