JPS5660023A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5660023A
JPS5660023A JP13544479A JP13544479A JPS5660023A JP S5660023 A JPS5660023 A JP S5660023A JP 13544479 A JP13544479 A JP 13544479A JP 13544479 A JP13544479 A JP 13544479A JP S5660023 A JPS5660023 A JP S5660023A
Authority
JP
Japan
Prior art keywords
substrate
film
semiconductor device
reverse side
nitriding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13544479A
Other languages
Japanese (ja)
Inventor
Masamitsu Yamauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP13544479A priority Critical patent/JPS5660023A/en
Publication of JPS5660023A publication Critical patent/JPS5660023A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To eliminate the variation of the characteristics of the subject semiconductor device due to an outward diffusion from the reverse side of the substrate by a method wherein, after an oxide film is formed on both sides of the substrate, a nitriding film is formed on its reverse side, a high temperature heat treatment process and then the nitriding film is removed. CONSTITUTION:Oxide films 3 and 4 are formed on the right and reverse sides of the substrate 2, which is an N<+> substrate with an N<-> layer superposed on it, and after a nitriding film 19 is formed on the oxide film 4 of the reverse side, a base region 7 and an emitter region 9 are formed by performing a multiple diffusion. After that, the nitriding film 19 is removed by performing a plasma etching or by using thermal phosphate. And after removing the oxide film 4, electrodes 10, 11 and 12 are formed. The formation instability of the base region 7 and the emitter region 9, due to the outward diffusion of the donor coming from the N<+> substrate when the high temperature heat treatment is performed, is hereby prevented and the semiconductor device for stabilized characteristics can be obtained.
JP13544479A 1979-10-20 1979-10-20 Manufacture of semiconductor device Pending JPS5660023A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13544479A JPS5660023A (en) 1979-10-20 1979-10-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13544479A JPS5660023A (en) 1979-10-20 1979-10-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5660023A true JPS5660023A (en) 1981-05-23

Family

ID=15151855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13544479A Pending JPS5660023A (en) 1979-10-20 1979-10-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5660023A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57194583A (en) * 1981-05-27 1982-11-30 Hitachi Ltd Mos semiconductor device and manufacture thereof
JPH0290609A (en) * 1988-09-28 1990-03-30 Fuji Electric Co Ltd Manufacture of semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50114169A (en) * 1974-02-15 1975-09-06
JPS50147664A (en) * 1974-05-17 1975-11-26

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50114169A (en) * 1974-02-15 1975-09-06
JPS50147664A (en) * 1974-05-17 1975-11-26

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57194583A (en) * 1981-05-27 1982-11-30 Hitachi Ltd Mos semiconductor device and manufacture thereof
JPH0290609A (en) * 1988-09-28 1990-03-30 Fuji Electric Co Ltd Manufacture of semiconductor device

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