JPS5673439A - Etching method - Google Patents

Etching method

Info

Publication number
JPS5673439A
JPS5673439A JP15030579A JP15030579A JPS5673439A JP S5673439 A JPS5673439 A JP S5673439A JP 15030579 A JP15030579 A JP 15030579A JP 15030579 A JP15030579 A JP 15030579A JP S5673439 A JPS5673439 A JP S5673439A
Authority
JP
Japan
Prior art keywords
substrate
plasma
etching
resist mask
intermittently
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15030579A
Other languages
Japanese (ja)
Inventor
Tsunehiro Naganami
Hiroshi Maruyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15030579A priority Critical patent/JPS5673439A/en
Publication of JPS5673439A publication Critical patent/JPS5673439A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent the heating-up of a substrate, to reduce the etching speed of a resist mask and to stabilize the etching process by a method wherein a plasma is generated intermittently. CONSTITUTION:When a plasma is generated intermittently, the temperature of a substrate is lower than that when it is generated continuously. Also, when the substrate temperature is high, the etching speed increases and a photo resist has a little larger temperature efficiency than Cr. Therefore, when the heating-up of the substrate is prevented by applying a resist mask on a Cr layer and generating the plasma intermittently, the etching speed becomes smaller than that it has been, and a stabilized etching of the Cr film can be performed using the resist mask having a uniform film thickness.
JP15030579A 1979-11-20 1979-11-20 Etching method Pending JPS5673439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15030579A JPS5673439A (en) 1979-11-20 1979-11-20 Etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15030579A JPS5673439A (en) 1979-11-20 1979-11-20 Etching method

Publications (1)

Publication Number Publication Date
JPS5673439A true JPS5673439A (en) 1981-06-18

Family

ID=15494092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15030579A Pending JPS5673439A (en) 1979-11-20 1979-11-20 Etching method

Country Status (1)

Country Link
JP (1) JPS5673439A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5954227A (en) * 1982-09-21 1984-03-29 Tokyo Denshi Kagaku Kabushiki Dry type pattern forming method
JP2009520356A (en) * 2005-12-16 2009-05-21 エリコン ユーエスエイ、インコーポレイテッド Method for etching a substrate for photolithography

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5954227A (en) * 1982-09-21 1984-03-29 Tokyo Denshi Kagaku Kabushiki Dry type pattern forming method
JP2009520356A (en) * 2005-12-16 2009-05-21 エリコン ユーエスエイ、インコーポレイテッド Method for etching a substrate for photolithography

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