JPS56137633A - Pattern forming - Google Patents

Pattern forming

Info

Publication number
JPS56137633A
JPS56137633A JP4090080A JP4090080A JPS56137633A JP S56137633 A JPS56137633 A JP S56137633A JP 4090080 A JP4090080 A JP 4090080A JP 4090080 A JP4090080 A JP 4090080A JP S56137633 A JPS56137633 A JP S56137633A
Authority
JP
Japan
Prior art keywords
pattern
resist
width
space
microlinear
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4090080A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6346972B2 (enrdf_load_stackoverflow
Inventor
Masaki Ito
Sotaro Edokoro
Hiroshi Gokan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4090080A priority Critical patent/JPS56137633A/ja
Publication of JPS56137633A publication Critical patent/JPS56137633A/ja
Publication of JPS6346972B2 publication Critical patent/JPS6346972B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Bipolar Transistors (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP4090080A 1980-03-28 1980-03-28 Pattern forming Granted JPS56137633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4090080A JPS56137633A (en) 1980-03-28 1980-03-28 Pattern forming

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4090080A JPS56137633A (en) 1980-03-28 1980-03-28 Pattern forming

Publications (2)

Publication Number Publication Date
JPS56137633A true JPS56137633A (en) 1981-10-27
JPS6346972B2 JPS6346972B2 (enrdf_load_stackoverflow) 1988-09-20

Family

ID=12593381

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4090080A Granted JPS56137633A (en) 1980-03-28 1980-03-28 Pattern forming

Country Status (1)

Country Link
JP (1) JPS56137633A (enrdf_load_stackoverflow)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6265333A (ja) * 1985-09-17 1987-03-24 Nippon Telegr & Teleph Corp <Ntt> 段差付エツチング法
JPS62102531A (ja) * 1985-10-29 1987-05-13 Sony Corp エツチング方法
JPS63110654A (ja) * 1986-10-28 1988-05-16 Sony Corp エツチング方法
JP2005252165A (ja) * 2004-03-08 2005-09-15 Semiconductor Leading Edge Technologies Inc パターン形成方法
JP2007258419A (ja) * 2006-03-23 2007-10-04 Toppan Printing Co Ltd インプリント用モールドの製造方法
JP2012190827A (ja) * 2011-03-08 2012-10-04 Toppan Printing Co Ltd インプリントモールド及びその作製方法、パターン形成体

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6265333A (ja) * 1985-09-17 1987-03-24 Nippon Telegr & Teleph Corp <Ntt> 段差付エツチング法
JPS62102531A (ja) * 1985-10-29 1987-05-13 Sony Corp エツチング方法
JPS63110654A (ja) * 1986-10-28 1988-05-16 Sony Corp エツチング方法
JP2005252165A (ja) * 2004-03-08 2005-09-15 Semiconductor Leading Edge Technologies Inc パターン形成方法
JP2007258419A (ja) * 2006-03-23 2007-10-04 Toppan Printing Co Ltd インプリント用モールドの製造方法
JP2012190827A (ja) * 2011-03-08 2012-10-04 Toppan Printing Co Ltd インプリントモールド及びその作製方法、パターン形成体

Also Published As

Publication number Publication date
JPS6346972B2 (enrdf_load_stackoverflow) 1988-09-20

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