JPS5610930A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5610930A
JPS5610930A JP8677479A JP8677479A JPS5610930A JP S5610930 A JPS5610930 A JP S5610930A JP 8677479 A JP8677479 A JP 8677479A JP 8677479 A JP8677479 A JP 8677479A JP S5610930 A JPS5610930 A JP S5610930A
Authority
JP
Japan
Prior art keywords
pattern
layer
photoresist
etched
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8677479A
Other languages
Japanese (ja)
Inventor
Mototsugu Ogura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP8677479A priority Critical patent/JPS5610930A/en
Publication of JPS5610930A publication Critical patent/JPS5610930A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To obtain an inexpensive microscopic resist pattern by a method wherein when a layer to be etched is patterned on a semiconductor substrate, the first and second photoresist patterns are formed so that the latter may be put on the former and the openings are provided at their end parts. CONSTITUTION:When the semiconductor substrate 1 is coated with the layer 2 to be etched and a minute pattern is formed on it, the first photoresist pattern 3, which has a fixed pattern, is formed on the layer 2. Next a heat-treatment or plasma- treatment is is given to the entire surface to harden the pattern 3, the next photoresist 4 is applied to the whole surface and is developed after prebaking, and the resist pattern 5 is formed by using a mask so that it may overlap the pattern 3. Here an opening to expose the layer 2 is provided by using the end part of the patterns 3 and 5. In this way, the dimension of the opening can be made 1-2mum, accordingly the pattern that is to be formed on the layer 2 can also be made minute.
JP8677479A 1979-07-09 1979-07-09 Manufacture of semiconductor device Pending JPS5610930A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8677479A JPS5610930A (en) 1979-07-09 1979-07-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8677479A JPS5610930A (en) 1979-07-09 1979-07-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5610930A true JPS5610930A (en) 1981-02-03

Family

ID=13896091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8677479A Pending JPS5610930A (en) 1979-07-09 1979-07-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5610930A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5860539A (en) * 1981-10-06 1983-04-11 Fujitsu Ltd Patterning method for positive resist
US4591547A (en) * 1982-10-20 1986-05-27 General Instrument Corporation Dual layer positive photoresist process and devices
US4686759A (en) * 1983-09-23 1987-08-18 U.S. Philips Corporation Method of manufacturing a semiconductor device
JP2001060003A (en) * 1999-06-29 2001-03-06 Hyundai Electronics Ind Co Ltd Photomask and method for forming fine pattern of semiconductor device using the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55138839A (en) * 1979-04-17 1980-10-30 Nec Kyushu Ltd Method of fabricating semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55138839A (en) * 1979-04-17 1980-10-30 Nec Kyushu Ltd Method of fabricating semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5860539A (en) * 1981-10-06 1983-04-11 Fujitsu Ltd Patterning method for positive resist
US4591547A (en) * 1982-10-20 1986-05-27 General Instrument Corporation Dual layer positive photoresist process and devices
US4686759A (en) * 1983-09-23 1987-08-18 U.S. Philips Corporation Method of manufacturing a semiconductor device
US4831425A (en) * 1983-09-23 1989-05-16 U.S. Philips Corp. Integrated circuit having improved contact region
JP2001060003A (en) * 1999-06-29 2001-03-06 Hyundai Electronics Ind Co Ltd Photomask and method for forming fine pattern of semiconductor device using the same

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