JPS56107554A - Formation of pattern - Google Patents

Formation of pattern

Info

Publication number
JPS56107554A
JPS56107554A JP907380A JP907380A JPS56107554A JP S56107554 A JPS56107554 A JP S56107554A JP 907380 A JP907380 A JP 907380A JP 907380 A JP907380 A JP 907380A JP S56107554 A JPS56107554 A JP S56107554A
Authority
JP
Japan
Prior art keywords
photoresist
pattern
stroke width
etched
developed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP907380A
Other languages
Japanese (ja)
Inventor
Masaki Ito
Hiroshi Gokan
Sotaro Edokoro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP907380A priority Critical patent/JPS56107554A/en
Publication of JPS56107554A publication Critical patent/JPS56107554A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To obtain a highly accurate submicron stroke width by a method wherein the first photoresist pattern is formed at equal intervals and then the second photoresist pattern desired is formed on the first pattern before being etched and both the photoresist are removed. CONSTITUTION:In the method for the formation of a pattern to provide a stroke width for a submicron region on a semiconductor element, a semiconductor substrate 1 is coated with photoresist 3 for electron beams and a pattern drawn at equal intervals is exposed to the electron beams 4 before being developed to form an opening 10. The surface produced is covered with photoresist 11 and exposed to light according to the pattern desired. The photoresist 11 is developed to form the opening 13 desired. With the electron beam photoresist 3 and the photoresist 11 as a mask, the photoresist surface is etched to form concave portions 14, 15 on the substrate 1 and then the electron beam photoresist 3 and the photoresist 11 are removed. By so doing, it is made possible to form a pattern with a highly accurate stroke width against various design patterns.
JP907380A 1980-01-29 1980-01-29 Formation of pattern Pending JPS56107554A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP907380A JPS56107554A (en) 1980-01-29 1980-01-29 Formation of pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP907380A JPS56107554A (en) 1980-01-29 1980-01-29 Formation of pattern

Publications (1)

Publication Number Publication Date
JPS56107554A true JPS56107554A (en) 1981-08-26

Family

ID=11710425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP907380A Pending JPS56107554A (en) 1980-01-29 1980-01-29 Formation of pattern

Country Status (1)

Country Link
JP (1) JPS56107554A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005252165A (en) * 2004-03-08 2005-09-15 Semiconductor Leading Edge Technologies Inc Pattern forming method
DE102005051972B4 (en) * 2005-10-31 2012-05-31 Infineon Technologies Ag Combined electron beam and optical lithography process

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005252165A (en) * 2004-03-08 2005-09-15 Semiconductor Leading Edge Technologies Inc Pattern forming method
JP4480424B2 (en) * 2004-03-08 2010-06-16 富士通マイクロエレクトロニクス株式会社 Pattern formation method
DE102005051972B4 (en) * 2005-10-31 2012-05-31 Infineon Technologies Ag Combined electron beam and optical lithography process

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