JPS56137630A - Pattern forming - Google Patents

Pattern forming

Info

Publication number
JPS56137630A
JPS56137630A JP4089780A JP4089780A JPS56137630A JP S56137630 A JPS56137630 A JP S56137630A JP 4089780 A JP4089780 A JP 4089780A JP 4089780 A JP4089780 A JP 4089780A JP S56137630 A JPS56137630 A JP S56137630A
Authority
JP
Japan
Prior art keywords
pattern
space
resist
exposure
create
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4089780A
Other languages
Japanese (ja)
Other versions
JPH0117247B2 (en
Inventor
Masaki Ito
Sotaro Edokoro
Hiroshi Gokan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4089780A priority Critical patent/JPS56137630A/en
Publication of JPS56137630A publication Critical patent/JPS56137630A/en
Publication of JPH0117247B2 publication Critical patent/JPH0117247B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Bipolar Transistors (AREA)
  • Weting (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To obtain an extreme microlinear width pattern by providing the first pattern with a wider space than a pattern of line and space, on the latter and creating the second pattern whose space is wider than the original one through the processing of an overlapped portion of the space in a concave or convex fashion. CONSTITUTION:A resist 3 is applied on an object to be processed on a substrate 1 and then a space is created by means of exposure and development with the help of an electronic beam 4. Another resist 11 is applied to create a space 13 through exposure and development. Following this process, a material 2 is etched using the resists 3 and 11 as a mask and then the mask 3, 11 is removed. Next, a regist 15 is applied to carry out an exposure 16 and development process to create a pattern 17. With the assistance of a resist mask 15, the material 2 is etched to create concave parts 18, 19, removing the resist 15. The pattern thus obtained is partially changed by a pattern 17 which is set by a logic product of spaces 10, 13, into a region. The groove widths of the concave parts 18, 19 are equal to each other. In this way, it is possible to form even patterns whose linear width is variegated or whose density varies, with satisfactory linear width precision.
JP4089780A 1980-03-28 1980-03-28 Pattern forming Granted JPS56137630A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4089780A JPS56137630A (en) 1980-03-28 1980-03-28 Pattern forming

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4089780A JPS56137630A (en) 1980-03-28 1980-03-28 Pattern forming

Publications (2)

Publication Number Publication Date
JPS56137630A true JPS56137630A (en) 1981-10-27
JPH0117247B2 JPH0117247B2 (en) 1989-03-29

Family

ID=12593295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4089780A Granted JPS56137630A (en) 1980-03-28 1980-03-28 Pattern forming

Country Status (1)

Country Link
JP (1) JPS56137630A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005252165A (en) * 2004-03-08 2005-09-15 Semiconductor Leading Edge Technologies Inc Pattern forming method
JP2007258419A (en) * 2006-03-23 2007-10-04 Toppan Printing Co Ltd Method of manufacturing imprinting mold

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005252165A (en) * 2004-03-08 2005-09-15 Semiconductor Leading Edge Technologies Inc Pattern forming method
JP4480424B2 (en) * 2004-03-08 2010-06-16 富士通マイクロエレクトロニクス株式会社 Pattern formation method
JP2007258419A (en) * 2006-03-23 2007-10-04 Toppan Printing Co Ltd Method of manufacturing imprinting mold

Also Published As

Publication number Publication date
JPH0117247B2 (en) 1989-03-29

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