JPS5553460A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS5553460A
JPS5553460A JP12700778A JP12700778A JPS5553460A JP S5553460 A JPS5553460 A JP S5553460A JP 12700778 A JP12700778 A JP 12700778A JP 12700778 A JP12700778 A JP 12700778A JP S5553460 A JPS5553460 A JP S5553460A
Authority
JP
Japan
Prior art keywords
layer
type
window
substrate
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12700778A
Other languages
Japanese (ja)
Inventor
Katsuhiko Suyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12700778A priority Critical patent/JPS5553460A/en
Publication of JPS5553460A publication Critical patent/JPS5553460A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide IC device having high switching speed and high voltage gain by forming the same conductive type high resistance layer and electric conductive layer as channels on a substrate and forming FET of enhancement and depression types. CONSTITUTION:N-type GaAs high resistance layer 2, n-type GaAs electrical conductive layer 3 are stacked on a semi insulative GaAs substrate 1 and the layer 3 is photoetched into mesa form and Au.Ge source, drain electrodes S, D are selectively formed and heat treated to metalize with the layer 3. Window 3E is provided on the layer 3 of gate part and coated with CVDSiO24 and window 3E is again opened and another window 3D is provided on other gate part. Gate film oxide 5E, 5D are formed by plasma oxidation method and the like through the windows 3E, 3D and Al electrodes 6E, 6D are attached. Thus, enhancement type FET as making the layer 2 channel and depression type FET as making the layer 3 channel are formed on a same substrate and a device of E/D system having high ability can be obtained.
JP12700778A 1978-10-16 1978-10-16 Semiconductor integrated circuit Pending JPS5553460A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12700778A JPS5553460A (en) 1978-10-16 1978-10-16 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12700778A JPS5553460A (en) 1978-10-16 1978-10-16 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5553460A true JPS5553460A (en) 1980-04-18

Family

ID=14949370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12700778A Pending JPS5553460A (en) 1978-10-16 1978-10-16 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5553460A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5654214A (en) * 1994-06-29 1997-08-05 U.S. Philips Corporation Method of manufacturing a semiconductor device having at least two field effect transistors with different pinch-off voltages

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5654214A (en) * 1994-06-29 1997-08-05 U.S. Philips Corporation Method of manufacturing a semiconductor device having at least two field effect transistors with different pinch-off voltages

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