JPS55154622A - Input and output managing system in multiprocessor system - Google Patents

Input and output managing system in multiprocessor system

Info

Publication number
JPS55154622A
JPS55154622A JP6288279A JP6288279A JPS55154622A JP S55154622 A JPS55154622 A JP S55154622A JP 6288279 A JP6288279 A JP 6288279A JP 6288279 A JP6288279 A JP 6288279A JP S55154622 A JPS55154622 A JP S55154622A
Authority
JP
Japan
Prior art keywords
unit
cpu2
instruction
cpu3
management
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6288279A
Other languages
Japanese (ja)
Inventor
Hiroaki Yokomichi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6288279A priority Critical patent/JPS55154622A/en
Publication of JPS55154622A publication Critical patent/JPS55154622A/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)

Abstract

PURPOSE: To easily enable to know the managing state of I/O units, by giving instructions to the I/O units and judging whether the right of management of an I/O unit resides in a CPU or another CPU from the status to the instructions.
CONSTITUTION: An I/O unit 5 is managed with a CPU2, and when the line connection instruction is given from the CPU2 to a communication control unit 4, the unit 4 returns normal status after the processing of the instruction and the management of the unit 5 is transferred to a CPU3. Next, the connection instruction is given from the CPU3 to the unit 4, the unit 4 returns the processing status of the instruction and the CPU3 judges that the management of the unit 5 is transferred to itself. Further, when the CPU3 given the connection instruction to the unit 4 before the CPU2 gives it to the unit 4, after the processing of the instruction is executed, a special status indicating that the unit 5 is still managed with the CPU2, is returned to the CPU2. Thus, the management state of I/O units can easily be known for the multiprocessor.
COPYRIGHT: (C)1980,JPO&Japio
JP6288279A 1979-05-22 1979-05-22 Input and output managing system in multiprocessor system Pending JPS55154622A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6288279A JPS55154622A (en) 1979-05-22 1979-05-22 Input and output managing system in multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6288279A JPS55154622A (en) 1979-05-22 1979-05-22 Input and output managing system in multiprocessor system

Publications (1)

Publication Number Publication Date
JPS55154622A true JPS55154622A (en) 1980-12-02

Family

ID=13213072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6288279A Pending JPS55154622A (en) 1979-05-22 1979-05-22 Input and output managing system in multiprocessor system

Country Status (1)

Country Link
JP (1) JPS55154622A (en)

Similar Documents

Publication Publication Date Title
JPS5443644A (en) Processing system for deadlock automatic release at exclusive control time
JPS55134459A (en) Data processing system
JPS5622160A (en) Data processing system having additional processor
JPS55154622A (en) Input and output managing system in multiprocessor system
JPS5680722A (en) Interprocessor control system
JPS55164922A (en) Multimicrocomputer
JPS57174747A (en) Device diagnosing system
JPS57178553A (en) Multiprocessor system
JPS52105741A (en) Input and output sharing device
JPS5635254A (en) Processor back-up system
JPS5696337A (en) Resource control system
JPS5717058A (en) Control system of microprogram
JPS5493340A (en) Duplex processing system
JPS55116156A (en) Multiple access unit for external memory unit
JPS5727322A (en) Input and output controlling system of computer
JPS5672753A (en) Selective processor for occupation of common bus line
JPS55105729A (en) Data processing unit
JPS57109022A (en) Control system for common signal bus
JPS57193842A (en) Request conflict detecting system
JPS5559526A (en) Inter-processor data exchange system
JPS5663657A (en) Memory switching system
JPS55108068A (en) Memory control system
JPS5561858A (en) Central operation control unit
JPS5638657A (en) Multiprocessor control system
JPS5520565A (en) Computer system