JPS55134934A - Projection exposing method - Google Patents

Projection exposing method

Info

Publication number
JPS55134934A
JPS55134934A JP4341779A JP4341779A JPS55134934A JP S55134934 A JPS55134934 A JP S55134934A JP 4341779 A JP4341779 A JP 4341779A JP 4341779 A JP4341779 A JP 4341779A JP S55134934 A JPS55134934 A JP S55134934A
Authority
JP
Japan
Prior art keywords
wafer
points
sample base
marks
representation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4341779A
Other languages
Japanese (ja)
Inventor
Kyusaku Nishioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP4341779A priority Critical patent/JPS55134934A/en
Publication of JPS55134934A publication Critical patent/JPS55134934A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To improve positioning accuracy and increase working speed by selecting several representation points at the desired positions of a wafer on a sample base, positioning the wafer and memorizing the amounts of position correction for the points, moving the sample base based on the memory and forming the image of a mask pattern on the wafer and exposing it. CONSTITUTION:On the surface of a wafer mounted on a sample base, plural marks 1-32 divided in square forms are put and marks 6, 9, 24, 27 among them which are at symmetrical positions are selected as representation points. Next, the wafer is positioned using these points and the amounts of position correction for the representation points are memorized, and then moving the sample base to marks near these representation points and correcting the position of the wafer, the wafer is exposed to the mark points sequentially. By so forming a mask pattern over the entire surface repeating divided exposure to the wafer, movement of the sample base is reduced and pattern accuracy is improved and also projection exposing speed is increased.
JP4341779A 1979-04-09 1979-04-09 Projection exposing method Pending JPS55134934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4341779A JPS55134934A (en) 1979-04-09 1979-04-09 Projection exposing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4341779A JPS55134934A (en) 1979-04-09 1979-04-09 Projection exposing method

Publications (1)

Publication Number Publication Date
JPS55134934A true JPS55134934A (en) 1980-10-21

Family

ID=12663129

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4341779A Pending JPS55134934A (en) 1979-04-09 1979-04-09 Projection exposing method

Country Status (1)

Country Link
JP (1) JPS55134934A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57113224A (en) * 1980-12-29 1982-07-14 Seiko Epson Corp Manufacture of semiconductor integrated circuit
JPS5828748A (en) * 1981-08-13 1983-02-19 Nippon Kogaku Kk <Nikon> Positioning device for transcribing device
US4610940A (en) * 1983-10-17 1986-09-09 Fujitsu Limited Method for fabricating a photomask pattern
JPS63158404A (en) * 1987-08-10 1988-07-01 Nikon Corp Position-aligning device in transfer apparatus

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57113224A (en) * 1980-12-29 1982-07-14 Seiko Epson Corp Manufacture of semiconductor integrated circuit
JPS5828748A (en) * 1981-08-13 1983-02-19 Nippon Kogaku Kk <Nikon> Positioning device for transcribing device
US4610940A (en) * 1983-10-17 1986-09-09 Fujitsu Limited Method for fabricating a photomask pattern
JPS63158404A (en) * 1987-08-10 1988-07-01 Nikon Corp Position-aligning device in transfer apparatus
JPH0410208B2 (en) * 1987-08-10 1992-02-24

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