JPS5490981A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5490981A
JPS5490981A JP13559878A JP13559878A JPS5490981A JP S5490981 A JPS5490981 A JP S5490981A JP 13559878 A JP13559878 A JP 13559878A JP 13559878 A JP13559878 A JP 13559878A JP S5490981 A JPS5490981 A JP S5490981A
Authority
JP
Japan
Prior art keywords
film
polycrystal
load
region
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13559878A
Other languages
Japanese (ja)
Other versions
JPS5927100B2 (en
Inventor
Takashi Hirao
Takashi Osone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP53135598A priority Critical patent/JPS5927100B2/en
Publication of JPS5490981A publication Critical patent/JPS5490981A/en
Publication of JPS5927100B2 publication Critical patent/JPS5927100B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To establish the device enabling high speed operation at low voltages, by constituting the inverter circuit with the polycrystal Si resistor including impurity, Si gate MOSFET, and the resistance lead region having the same degree of resistance as the gate of FET, and by taking the polycrystal Si resistor as the load of FET. CONSTITUTION:The field SiO2 film 2 is coated on the N type Si substrate 1, and the hole 3 is made on the Si gate MOSFET forming region. Next, the thin gate SiO2 film 4 is grown and the gate electrode of FET and the polycrystal Si film 5 being the load are deposited on the entire surface of the substrate 1, and it is covered with the SiO2 film 6. After that, the film 6 is remained as 6' only on the load region, etching is made by taking this as a mask, the polycrystal Si film 3 is left only on the film 4 and the load, and the diffusion windows 7 and 7' are opened. Next, the P<+> type source and drain regions 8 and 8', and the gate electrode 5', and the lead 5'' of resistance region are formed in the windows 7 and 7' by injecting impurity, and the high resistance region 9 is produced on the film 5 under the film 6'.
JP53135598A 1978-11-01 1978-11-01 semiconductor equipment Expired JPS5927100B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53135598A JPS5927100B2 (en) 1978-11-01 1978-11-01 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53135598A JPS5927100B2 (en) 1978-11-01 1978-11-01 semiconductor equipment

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP6217272A Division JPS5710578B2 (en) 1972-06-20 1972-06-20

Publications (2)

Publication Number Publication Date
JPS5490981A true JPS5490981A (en) 1979-07-19
JPS5927100B2 JPS5927100B2 (en) 1984-07-03

Family

ID=15155555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53135598A Expired JPS5927100B2 (en) 1978-11-01 1978-11-01 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS5927100B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS48112274U (en) * 1972-03-29 1973-12-22

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS48112274U (en) * 1972-03-29 1973-12-22

Also Published As

Publication number Publication date
JPS5927100B2 (en) 1984-07-03

Similar Documents

Publication Publication Date Title
JPS5688354A (en) Semiconductor integrated circuit device
JPS57192079A (en) Semiconductor device
JPS55151363A (en) Mos semiconductor device and fabricating method of the same
JPS5633881A (en) Manufacture of semiconductor device
JPS54156483A (en) Non-volatile semiconductor memory device
JPS5490981A (en) Semiconductor device
JPS57149774A (en) Semiconductor device
JPS55162270A (en) Semiconductor device
JPS5674939A (en) Preparation method of semiconductor integrated circuit
JPS56147466A (en) Semiconductor device
JPS5730368A (en) Tunnel fet
JPS54102982A (en) Charge transfer type semiconductor device
JPS5513953A (en) Complementary integrated circuit
JPS5629344A (en) Semiconductor integrated circuit device and manufacture thereof
JPS5748248A (en) Manufacture of semiconductor device
JPS57128957A (en) Semiconductor integrated circuit device and manufacture thereof
JPS54144182A (en) Semiconductor device
JPS54111792A (en) Semiconductor device and its manufacture
JPS5642372A (en) Manufacture of semiconductor device
JPS566464A (en) Semiconductor device and manufacture thereof
JPS56147467A (en) Cmos semiconductor device and manufacture thereof
JPS6465875A (en) Thin film transistor and manufacture thereof
JPS572579A (en) Manufacture of junction type field effect transistor
JPS5490979A (en) Integrated circuit
JPS57207373A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081221

Year of fee payment: 7

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081221

Year of fee payment: 7

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 8

Free format text: PAYMENT UNTIL: 20091221

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101221

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 9

Free format text: PAYMENT UNTIL: 20101221

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 10

Free format text: PAYMENT UNTIL: 20111221

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111221

Year of fee payment: 10

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 11

Free format text: PAYMENT UNTIL: 20121221

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121221

Year of fee payment: 11

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131221

Year of fee payment: 12