JPS5488076A - Manufacture for semiconductor device - Google Patents

Manufacture for semiconductor device

Info

Publication number
JPS5488076A
JPS5488076A JP15581877A JP15581877A JPS5488076A JP S5488076 A JPS5488076 A JP S5488076A JP 15581877 A JP15581877 A JP 15581877A JP 15581877 A JP15581877 A JP 15581877A JP S5488076 A JPS5488076 A JP S5488076A
Authority
JP
Japan
Prior art keywords
layer
film
bump
substrate
inserted metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15581877A
Other languages
Japanese (ja)
Inventor
Misao Saga
Akira Amano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP15581877A priority Critical patent/JPS5488076A/en
Publication of JPS5488076A publication Critical patent/JPS5488076A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To aviod the occurrence of contamination of the surface, by providing the open hole on the semiconductor substrate through coating SiO2 film and Si3N4 film, evaporating the inserted metal and the contact metal after lamination, and forming Ag bump after etching them.
CONSTITUTION: On the Si substrate 1 on which the diffusion region 4 is formed, the SiO2 film 2 being the surface protection film is coated, and after that, it is covered with the Si3N4 film 3, and window is opened on the region 4 with photo etching. Next, the Cr layer 5 being the contact metal and the Au layer 6 of inserted metal are evaporated on the entire surface with evaporation, and the Cr layer 5' and the Au layer 6' being the rear electrodes are coated on the rear side of the substrate 1 with lamination. After that, the inserted metal layer 6 and the contact metal layer 5 are sequentially photo etched, and the Ag bump of a given shape is formed on the Au inserted metal layer 6 with plating. Thus, since no photo resist mask is used at bump formation, the surface is not contaminated.
COPYRIGHT: (C)1979,JPO&Japio
JP15581877A 1977-12-24 1977-12-24 Manufacture for semiconductor device Pending JPS5488076A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15581877A JPS5488076A (en) 1977-12-24 1977-12-24 Manufacture for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15581877A JPS5488076A (en) 1977-12-24 1977-12-24 Manufacture for semiconductor device

Publications (1)

Publication Number Publication Date
JPS5488076A true JPS5488076A (en) 1979-07-12

Family

ID=15614140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15581877A Pending JPS5488076A (en) 1977-12-24 1977-12-24 Manufacture for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5488076A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5055262A (en) * 1973-09-12 1975-05-15
JPS5153143U (en) * 1974-10-22 1976-04-22
JPS51105266A (en) * 1975-03-13 1976-09-17 New Nippon Electric Co Handotaisochino seizohoho
JPS5259576A (en) * 1975-11-11 1977-05-17 Nec Corp Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5055262A (en) * 1973-09-12 1975-05-15
JPS5153143U (en) * 1974-10-22 1976-04-22
JPS51105266A (en) * 1975-03-13 1976-09-17 New Nippon Electric Co Handotaisochino seizohoho
JPS5259576A (en) * 1975-11-11 1977-05-17 Nec Corp Semiconductor device

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