JPS5459080A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5459080A
JPS5459080A JP12631877A JP12631877A JPS5459080A JP S5459080 A JPS5459080 A JP S5459080A JP 12631877 A JP12631877 A JP 12631877A JP 12631877 A JP12631877 A JP 12631877A JP S5459080 A JPS5459080 A JP S5459080A
Authority
JP
Japan
Prior art keywords
layer
vamp
reduction region
layers
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12631877A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6138612B2 (US07696358-20100413-C00002.png
Inventor
Susumu Sato
Hideo Tsunemitsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12631877A priority Critical patent/JPS5459080A/ja
Priority to US05/952,543 priority patent/US4244002A/en
Priority to FR7829713A priority patent/FR2406893A1/fr
Priority to DE2845612A priority patent/DE2845612C2/de
Publication of JPS5459080A publication Critical patent/JPS5459080A/ja
Publication of JPS6138612B2 publication Critical patent/JPS6138612B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/05001Internal layers
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    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
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    • H01L2224/05001Internal layers
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    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
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    • H01L2224/05644Gold [Au] as principal constituent
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    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
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    • H01L2224/83801Soldering or alloying
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    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Measuring Fluid Pressure (AREA)
JP12631877A 1977-10-19 1977-10-19 Semiconductor device Granted JPS5459080A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP12631877A JPS5459080A (en) 1977-10-19 1977-10-19 Semiconductor device
US05/952,543 US4244002A (en) 1977-10-19 1978-10-18 Semiconductor device having bump terminal electrodes
FR7829713A FR2406893A1 (fr) 1977-10-19 1978-10-18 Dispositif a semi-conducteur a electrodes de raccordement en saillie
DE2845612A DE2845612C2 (de) 1977-10-19 1978-10-19 Halbleiteranordnung mit höckerförmigen Anschlußelektroden

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12631877A JPS5459080A (en) 1977-10-19 1977-10-19 Semiconductor device

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP29689285A Division JPS6211252A (ja) 1985-12-27 1985-12-27 半導体装置
JP60296893A Division JPS6211253A (ja) 1985-12-27 1985-12-27 半導体装置

Publications (2)

Publication Number Publication Date
JPS5459080A true JPS5459080A (en) 1979-05-12
JPS6138612B2 JPS6138612B2 (US07696358-20100413-C00002.png) 1986-08-30

Family

ID=14932210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12631877A Granted JPS5459080A (en) 1977-10-19 1977-10-19 Semiconductor device

Country Status (4)

Country Link
US (1) US4244002A (US07696358-20100413-C00002.png)
JP (1) JPS5459080A (US07696358-20100413-C00002.png)
DE (1) DE2845612C2 (US07696358-20100413-C00002.png)
FR (1) FR2406893A1 (US07696358-20100413-C00002.png)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57170554A (en) * 1981-04-15 1982-10-20 Hitachi Ltd Semiconductor device
JPS593954A (ja) * 1982-06-29 1984-01-10 Mitsubishi Electric Corp 半導体装置

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5925387B2 (ja) * 1980-06-10 1984-06-16 株式会社東芝 半導体装置
IT1156085B (it) * 1982-10-25 1987-01-28 Cselt Centro Studi Lab Telecom Dispositivo optoelettronico e procedimento per la sua fabbricazione
DE3727488C2 (de) * 1987-08-18 1994-05-26 Telefunken Microelectron Optoelektronisches Bauelement
US4922322A (en) * 1989-02-09 1990-05-01 National Semiconductor Corporation Bump structure for reflow bonding of IC devices
US5208186A (en) * 1989-02-09 1993-05-04 National Semiconductor Corporation Process for reflow bonding of bumps in IC devices
JPH0437067A (ja) * 1990-05-31 1992-02-07 Canon Inc 半導体素子用電極及び該電極を有する半導体装置及びその製造方法
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
WO1996031905A1 (en) 1995-04-05 1996-10-10 Mcnc A solder bump structure for a microelectronic substrate
KR0145128B1 (ko) * 1995-04-24 1998-08-17 김광호 열방열 핀을 구비한 내부 리드 본딩 장치 및 이를 이용한 내부 리드 본딩 방법
US5617991A (en) * 1995-12-01 1997-04-08 Advanced Micro Devices, Inc. Method for electrically conductive metal-to-metal bonding
US6184581B1 (en) * 1997-11-24 2001-02-06 Delco Electronics Corporation Solder bump input/output pad for a surface mount circuit device
WO2002039802A2 (en) * 2000-11-10 2002-05-16 Unitive Electronics, Inc. Methods of positioning components using liquid prime movers and related structures
US6863209B2 (en) 2000-12-15 2005-03-08 Unitivie International Limited Low temperature methods of bonding components
US6960828B2 (en) 2002-06-25 2005-11-01 Unitive International Limited Electronic structures including conductive shunt layers
US7547623B2 (en) 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
US7531898B2 (en) * 2002-06-25 2009-05-12 Unitive International Limited Non-Circular via holes for bumping pads and related structures
TWI225899B (en) * 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer
US7049216B2 (en) * 2003-10-14 2006-05-23 Unitive International Limited Methods of providing solder structures for out plane connections
US7358174B2 (en) * 2004-04-13 2008-04-15 Amkor Technology, Inc. Methods of forming solder bumps on exposed metal pads
US20060205170A1 (en) * 2005-03-09 2006-09-14 Rinne Glenn A Methods of forming self-healing metal-insulator-metal (MIM) structures and related devices
US7674701B2 (en) 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US7932615B2 (en) * 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers
US8569886B2 (en) 2011-11-22 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of under bump metallization in packaging semiconductor devices
DE102014110473A1 (de) * 2014-07-24 2016-01-28 Osram Opto Semiconductors Gmbh Träger für ein elektrisches Bauelement
US10647133B2 (en) 2017-10-31 2020-05-12 Seiko Epson Corporation Medium transporting device and recording apparatus

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL87258C (US07696358-20100413-C00002.png) * 1969-01-15
DE2409312C3 (de) * 1974-02-27 1981-01-08 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Halbleiteranordnung mit einer auf der Halbleiteroberfläche angeordneten Metallschicht und Verfahren zu ihrer Herstellung
JPS51147253A (en) * 1975-06-13 1976-12-17 Nec Corp Structure of electrode terminal
JPS5851425B2 (ja) * 1975-08-22 1983-11-16 株式会社日立製作所 ハンドウタイソウチ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57170554A (en) * 1981-04-15 1982-10-20 Hitachi Ltd Semiconductor device
JPS593954A (ja) * 1982-06-29 1984-01-10 Mitsubishi Electric Corp 半導体装置

Also Published As

Publication number Publication date
US4244002A (en) 1981-01-06
DE2845612A1 (de) 1979-04-26
FR2406893A1 (fr) 1979-05-18
JPS6138612B2 (US07696358-20100413-C00002.png) 1986-08-30
DE2845612C2 (de) 1987-01-22
FR2406893B1 (US07696358-20100413-C00002.png) 1983-10-07

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