JPS54129888A - Semiconductor unit - Google Patents

Semiconductor unit

Info

Publication number
JPS54129888A
JPS54129888A JP3748678A JP3748678A JPS54129888A JP S54129888 A JPS54129888 A JP S54129888A JP 3748678 A JP3748678 A JP 3748678A JP 3748678 A JP3748678 A JP 3748678A JP S54129888 A JPS54129888 A JP S54129888A
Authority
JP
Japan
Prior art keywords
film
layer
coated
metal
insulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3748678A
Other languages
Japanese (ja)
Inventor
Masaru Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3748678A priority Critical patent/JPS54129888A/en
Publication of JPS54129888A publication Critical patent/JPS54129888A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make good the bondingness with metal film wiring and to increase the surface hardness, by using the lower layer film consisting of insulation resin as the surface protection film of semiconductor unit, intermediate layer film of metal, and three layer laminating film of the upper of insulation compound of metal.
CONSTITUTION: On the Si substrate 1, SiO2, Si3N4 or those composite film 2 is coated, opening is made on the diffusion region 3 placed on the substrate 1, and the ohmic contact layer 4 such as Pt-Si and Al-Si is coated to here. Further, the Al film 5 at the first layer wiring surrounded with the Al2O3 film 6 extended to the film 2 in contact with the layer 4 is formed, and the intermediate insulation film 7 consisting of SiO2, Si3O4 and polyimide is coated on it. After that, opening is made to a given region of the film 7, Ti film 8, Pt film 9 and Au film 10 of the two layer wiring are provided, and after forming the bump terminal 11, the Al film 12 and Al2O3 film 13 are provided via the insulation resin film, constituting the surface portection film.
COPYRIGHT: (C)1979,JPO&Japio
JP3748678A 1978-03-30 1978-03-30 Semiconductor unit Pending JPS54129888A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3748678A JPS54129888A (en) 1978-03-30 1978-03-30 Semiconductor unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3748678A JPS54129888A (en) 1978-03-30 1978-03-30 Semiconductor unit

Publications (1)

Publication Number Publication Date
JPS54129888A true JPS54129888A (en) 1979-10-08

Family

ID=12498840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3748678A Pending JPS54129888A (en) 1978-03-30 1978-03-30 Semiconductor unit

Country Status (1)

Country Link
JP (1) JPS54129888A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56165345A (en) * 1980-05-23 1981-12-18 Mitsubishi Electric Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56165345A (en) * 1980-05-23 1981-12-18 Mitsubishi Electric Corp Semiconductor device
JPS6257095B2 (en) * 1980-05-23 1987-11-30 Mitsubishi Electric Corp

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