JPS54131867A - Structure of projection electrode of semiconductor device - Google Patents

Structure of projection electrode of semiconductor device

Info

Publication number
JPS54131867A
JPS54131867A JP3944078A JP3944078A JPS54131867A JP S54131867 A JPS54131867 A JP S54131867A JP 3944078 A JP3944078 A JP 3944078A JP 3944078 A JP3944078 A JP 3944078A JP S54131867 A JPS54131867 A JP S54131867A
Authority
JP
Japan
Prior art keywords
electrode
plating
psg14
constitution
reliability
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3944078A
Other languages
Japanese (ja)
Inventor
Yoshiaki Komatsubara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3944078A priority Critical patent/JPS54131867A/en
Publication of JPS54131867A publication Critical patent/JPS54131867A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To prevent the crack occurrence of the protective film under the electrode lower layer by lessening the stress caused when the projection electrode is formed, and thus to insure the reliability at the wiring part.
CONSTITUTION: SiO212, Al wiring 13 and PSG14 are formed on Si substrate 11, and Cr15 and Cu16 of the fundation metal layer to be used as the diffusion barrier are deposited including the periphery of the opening of film 14 along with plating of Au17. Furthermore, Au projection electrode 18 is formed via the electrolytic plating on auxiliary electrode 17 in a narrower area than electrode 17. In such constitution, a large-area auxiliary electrode layer 17 and the foundation metal layer extend between electrode 18 and PSG14 when electrode 18 is formed through plating to eliminate concentration of the stress to PSG. As a result, no crack is caused, and thus the protection effect has no deterioration for the PSG film. Thus, the reliability is never lowered.
COPYRIGHT: (C)1979,JPO&Japio
JP3944078A 1978-04-04 1978-04-04 Structure of projection electrode of semiconductor device Pending JPS54131867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3944078A JPS54131867A (en) 1978-04-04 1978-04-04 Structure of projection electrode of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3944078A JPS54131867A (en) 1978-04-04 1978-04-04 Structure of projection electrode of semiconductor device

Publications (1)

Publication Number Publication Date
JPS54131867A true JPS54131867A (en) 1979-10-13

Family

ID=12553061

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3944078A Pending JPS54131867A (en) 1978-04-04 1978-04-04 Structure of projection electrode of semiconductor device

Country Status (1)

Country Link
JP (1) JPS54131867A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5294486A (en) * 1990-10-22 1994-03-15 International Business Machines Corporation Barrier improvement in thin films
US5316974A (en) * 1988-12-19 1994-05-31 Texas Instruments Incorporated Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5316974A (en) * 1988-12-19 1994-05-31 Texas Instruments Incorporated Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer
US5294486A (en) * 1990-10-22 1994-03-15 International Business Machines Corporation Barrier improvement in thin films

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