JPS5574159A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5574159A
JPS5574159A JP14744878A JP14744878A JPS5574159A JP S5574159 A JPS5574159 A JP S5574159A JP 14744878 A JP14744878 A JP 14744878A JP 14744878 A JP14744878 A JP 14744878A JP S5574159 A JPS5574159 A JP S5574159A
Authority
JP
Japan
Prior art keywords
layer
wiring
pattern
wiring pattern
cracks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14744878A
Other languages
Japanese (ja)
Other versions
JPS6050334B2 (en
Inventor
Hiroyasu Karimoto
Kosei Kajiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP53147448A priority Critical patent/JPS6050334B2/en
Publication of JPS5574159A publication Critical patent/JPS5574159A/en
Publication of JPS6050334B2 publication Critical patent/JPS6050334B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To prevent Al wiring from breaking by allowing barrier metal layer pattern to remain covering the Al wiring pattern to prevent etching solution from penetrating through cracks of CVD oxide film.
CONSTITUTION: A diffusion layer 2 is formed on the main surface of Si substrate. Al wiring pattern 4 is selectively formed on the layer 2 and the SiO2 layer 3, with openings 13 on the layer 3. The layer 2 and the Al wiring pattern 4 are ohmically connected by sintering process in N2, then CVD SiO2 layer 6 is deposited. This layer 6 is liable to cause cracks. Next, the Cr-Cu layer 7 having openings 16 is formed on the layer 6. The protruded electrode 5 is formed by Au plating by use of resist mask 8. The mask 8 is removed, the electrode 5 and the layer 7 are selectively convered with resist mask 9 having a larger area than the pattern 4, and the layer 7 is etched away. The structure allows the barrier metal layer 7 to completely cover the Al wiring pattern 4, thereby effectively preventing etching solution from penetrating through cracks of CVD SiO2. Thus, the Al wiring is protected.
COPYRIGHT: (C)1980,JPO&Japio
JP53147448A 1978-11-28 1978-11-28 semiconductor equipment Expired JPS6050334B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53147448A JPS6050334B2 (en) 1978-11-28 1978-11-28 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53147448A JPS6050334B2 (en) 1978-11-28 1978-11-28 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS5574159A true JPS5574159A (en) 1980-06-04
JPS6050334B2 JPS6050334B2 (en) 1985-11-08

Family

ID=15430570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53147448A Expired JPS6050334B2 (en) 1978-11-28 1978-11-28 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6050334B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5868949A (en) * 1981-10-20 1983-04-25 Matsushita Electric Ind Co Ltd Semiconductor device
US7218008B2 (en) 2003-06-30 2007-05-15 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5868949A (en) * 1981-10-20 1983-04-25 Matsushita Electric Ind Co Ltd Semiconductor device
JPS628031B2 (en) * 1981-10-20 1987-02-20 Matsushita Electric Ind Co Ltd
US7218008B2 (en) 2003-06-30 2007-05-15 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
US7981792B2 (en) 2003-06-30 2011-07-19 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument

Also Published As

Publication number Publication date
JPS6050334B2 (en) 1985-11-08

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