JPS54113275A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54113275A
JPS54113275A JP1988278A JP1988278A JPS54113275A JP S54113275 A JPS54113275 A JP S54113275A JP 1988278 A JP1988278 A JP 1988278A JP 1988278 A JP1988278 A JP 1988278A JP S54113275 A JPS54113275 A JP S54113275A
Authority
JP
Japan
Prior art keywords
layer
top layer
type layer
film
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988278A
Other languages
Japanese (ja)
Inventor
Masayuki Asaka
Minoru Azuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1988278A priority Critical patent/JPS54113275A/en
Publication of JPS54113275A publication Critical patent/JPS54113275A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To aviod the deformation of the edge of the top layer to reduce a leak current by subjecting the top layer to the sand blast process after covering the top layer with a film, where an Al film and a PSG film are laminated, when a gate turn-off thyristor is constituted to form a bevel face in the side face.
CONSTITUTION: N-type layer 3 to be a base region is provided on P-type layer 4 to be an anode region, and P-type layer 2 to be a gate region is formed on layer 3, and N-type layer 1 to be a cathode region is provided in layer 2, thereby constituting a gate turn-off thyristor. After that, though side faces of these layers are subjected to sand blast to form a bevel face, the edge of N-type layer 1 of the top layer is deformed. For the purpose of preventing this deformation, Al layer 15 is caused to adhere to the top layer and is covered with hard insulating film 16 such as PSG, and the sand blast process is performed. As a result, the side edge of the substrate is prevented from breaking, and the leak current is reduced.
COPYRIGHT: (C)1979,JPO&Japio
JP1988278A 1978-02-24 1978-02-24 Semiconductor device Pending JPS54113275A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988278A JPS54113275A (en) 1978-02-24 1978-02-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988278A JPS54113275A (en) 1978-02-24 1978-02-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS54113275A true JPS54113275A (en) 1979-09-04

Family

ID=12011572

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988278A Pending JPS54113275A (en) 1978-02-24 1978-02-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54113275A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57139962A (en) * 1981-02-25 1982-08-30 Nec Corp Semiconductor device
JPS6235568A (en) * 1985-08-08 1987-02-16 Mitsubishi Electric Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57139962A (en) * 1981-02-25 1982-08-30 Nec Corp Semiconductor device
JPS6235568A (en) * 1985-08-08 1987-02-16 Mitsubishi Electric Corp Semiconductor device

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