JPS5522856A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

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Publication number
JPS5522856A
JPS5522856A JP9603378A JP9603378A JPS5522856A JP S5522856 A JPS5522856 A JP S5522856A JP 9603378 A JP9603378 A JP 9603378A JP 9603378 A JP9603378 A JP 9603378A JP S5522856 A JPS5522856 A JP S5522856A
Authority
JP
Japan
Prior art keywords
layer
film
successively
high density
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9603378A
Other languages
Japanese (ja)
Inventor
Shiyouji Ariizumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9603378A priority Critical patent/JPS5522856A/en
Publication of JPS5522856A publication Critical patent/JPS5522856A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To prevent occurrence of a leak current and raise an integration rate by meeting a source and drain layer a high density layer having a comparatively low density and further a high density layer having a high density in the vicinity of a field region.
CONSTITUTION: For example, insulation films 12 and 13 are formed on a semiconductor substarte 11 having a p-type conductiom mode. Successively, an insulatiom film 14 is formed thereon. Next, the film 14 is opened by a resist film 15 selectively formed. Successively, an opening of the film is formed wider than that of the film 14 on the film 13. Successively, the p++ layer 18 is formed by injecting the impurity from the opening of the film 14. Successively, after removing the films 14, the P+ layer 19 is formed by injecting the impurity from the opening 17. Successively, a field insulated layer film 20 is formed by oxidizing the substrate 11. Next, a gate electrode 22, gate insulated film 21, source and drain layer 23 and 24 are formed. According to such a process, a resistance to voltage is not lowered because these layers 23 and 24 may met the layer 19 having a comparatively low density. Because the layer 18 having a comparatively high density exists in the vicinity of a center of the layer 20, a leak is not caused. Therefore, the integration rate can be improved.
COPYRIGHT: (C)1980,JPO&Japio
JP9603378A 1978-08-07 1978-08-07 Semiconductor device and its manufacturing method Pending JPS5522856A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9603378A JPS5522856A (en) 1978-08-07 1978-08-07 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9603378A JPS5522856A (en) 1978-08-07 1978-08-07 Semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JPS5522856A true JPS5522856A (en) 1980-02-18

Family

ID=14154111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9603378A Pending JPS5522856A (en) 1978-08-07 1978-08-07 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JPS5522856A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5710247A (en) * 1980-06-23 1982-01-19 Nec Corp Semiconductor device
US5023191A (en) * 1988-12-01 1991-06-11 Fuji Electric Co., Ltd. Method of producing a semiconductor device using a single mask method for providing multiple masking patterns
US5116775A (en) * 1986-06-18 1992-05-26 Hitachi, Ltd. Method of producing semiconductor memory device with buried barrier layer
US5373177A (en) * 1992-10-01 1994-12-13 Nec Corporation Semiconductor device with improved electric charge storage characteristics
US5686347A (en) * 1994-12-27 1997-11-11 United Microelectronics Corporation Self isolation manufacturing method
US5773336A (en) * 1995-12-30 1998-06-30 Samsung Electronics Co., Ltd. Methods of forming semiconductor active regions having channel-stop isolation regions therein
US5786265A (en) * 1995-05-12 1998-07-28 Samsung Electronics Co., Ltd. Methods of forming integrated semiconductor devices having improved channel-stop regions therein, and devices formed thereby

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5331979A (en) * 1976-09-06 1978-03-25 Nec Corp Insulated gate type field effect semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5331979A (en) * 1976-09-06 1978-03-25 Nec Corp Insulated gate type field effect semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5710247A (en) * 1980-06-23 1982-01-19 Nec Corp Semiconductor device
JPS6320382B2 (en) * 1980-06-23 1988-04-27 Nippon Electric Co
US5116775A (en) * 1986-06-18 1992-05-26 Hitachi, Ltd. Method of producing semiconductor memory device with buried barrier layer
US5023191A (en) * 1988-12-01 1991-06-11 Fuji Electric Co., Ltd. Method of producing a semiconductor device using a single mask method for providing multiple masking patterns
US5373177A (en) * 1992-10-01 1994-12-13 Nec Corporation Semiconductor device with improved electric charge storage characteristics
US5686347A (en) * 1994-12-27 1997-11-11 United Microelectronics Corporation Self isolation manufacturing method
US5786265A (en) * 1995-05-12 1998-07-28 Samsung Electronics Co., Ltd. Methods of forming integrated semiconductor devices having improved channel-stop regions therein, and devices formed thereby
US5773336A (en) * 1995-12-30 1998-06-30 Samsung Electronics Co., Ltd. Methods of forming semiconductor active regions having channel-stop isolation regions therein

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