JPS6235568A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6235568A
JPS6235568A JP17603785A JP17603785A JPS6235568A JP S6235568 A JPS6235568 A JP S6235568A JP 17603785 A JP17603785 A JP 17603785A JP 17603785 A JP17603785 A JP 17603785A JP S6235568 A JPS6235568 A JP S6235568A
Authority
JP
Japan
Prior art keywords
outer periphery
protective film
main surface
semiconductor device
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17603785A
Other languages
Japanese (ja)
Inventor
Futoshi Tokuno
徳能 太
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17603785A priority Critical patent/JPS6235568A/en
Publication of JPS6235568A publication Critical patent/JPS6235568A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching

Abstract

PURPOSE:To form a preferable and effective positive bevel shape by forming a protective film for protecting the outer periphery of a semiconductor substrate against a blowing collision of polishing material powder on the outer periphery. CONSTITUTION:This is of the case adapted for an inverted conduction thyristor by outer peripheral gate type, and a protective film 7 is formed by means such as depositing, sputtering or plating through an oxide film 6 on the entire outer periphery of the second main surface of a semiconductor substrate 1 to coat the entire outer periphery separated from a gate electrode 4. The material of the film 7 needs to form directly on a silicon or through the film 6 at suffi ciently slow grinding speed as compared with the silicon of the substrate 1 in case of sand-blasting with polishing material powder, is preferably metal and particularly soft metal such as gold, silver, aluminum or copper to sufficient ly perform the purpose, and the thickness is suitably approx. 5-30mum.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置に関し、特に1方向に高耐圧が要
求される半導体装置におけるエレメント周辺部の改良構
造に係るものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to an improved structure around an element in a semiconductor device that requires high breakdown voltage in one direction.

〔従来の技術〕[Conventional technology]

従来例によるこの種の半導体装置として、特公昭57−
21867号公報に記載された装置構成、こ−では逆導
通サイリスタの断面構造を第5図および第6図に示す。
As a conventional semiconductor device of this type,
The cross-sectional structure of the device configuration described in Japanese Patent No. 21867, in this case a reverse conduction thyristor, is shown in FIGS. 5 and 6.

これらの各図において、符号1は半導体基板、2は半導
体基板1の第1の主面上に鑞材5で鑞付けされたアノー
ド電極板(支持電極板)、3および4は同第2の主面上
に形成されたカソード電極およびゲート電極であり、ま
たn、はnニミフタ領域、PBはpベース領域、rlB
はnベース領域、PEはpエミッタ領域である。
In each of these figures, reference numeral 1 indicates a semiconductor substrate, 2 indicates an anode electrode plate (supporting electrode plate) brazed with a solder material 5 on the first main surface of the semiconductor substrate 1, and 3 and 4 indicate the same second electrode plate. They are a cathode electrode and a gate electrode formed on the main surface, and n is an n-nimifta region, PB is a p base region, and rlB
is an n base region, and PE is a p emitter region.

こ\でこの種の半導体装置にあって、一般に高耐圧を得
るためには、pn接合面とウェハ端面とに成る角度の傾
斜を与えたベベル構造を導入するようにしているが、こ
のときのpn接合面と、これに隣接する高比抵抗層のウ
ェハ端面とのなす角度θは、ポジティブベベルの場合、
数十度が最適であり、またネガティブベベルの場合、数
度が最適であると言われている。
In this type of semiconductor device, generally, in order to obtain a high breakdown voltage, a bevel structure is introduced with an inclined angle between the pn junction surface and the wafer end surface. In the case of a positive bevel, the angle θ between the pn junction surface and the wafer end surface of the high resistivity layer adjacent thereto is:
It is said that tens of degrees is optimal, and in the case of negative bevel, several degrees is said to be optimal.

これらの各場合にあって、ポジティブベベルでは電圧印
加時の空乏層を18側(高比抵抗側)に、またネガティ
ブベベルでは電圧印加時の空乏層をPB側(低比抵抗側
)に、それぞれ積極的に大きく広げて表面電界を弱める
ようにしており、高耐圧化をなす上で、両者共、その空
乏層を広げるために、ウェハ端面の沿面距離を大きくと
ることが必要であるが、ネガティブベベルの場合には、
ポジティブベベルの場合に比較して、前記角度0が極め
て小さいことから、ベベル構造のためにとらなければな
らないウニ八周辺部の面積が必然的に大きくなって、ウ
ェハの有効利用率の面から不利であり、またベベル角度
θについても、ネガティブベベルの場合には、高耐圧化
に伴ってさらに小さくしなければならず、同角度θの制
御の面でポジティブへベルの場合に比較するときに不利
となるもので、これらの事柄から従来は、高耐圧化なら
びにウェハの有効利用率向上のために、そのJ2接合に
一ついても、一般的にポジティブへベルによる第5図お
よび第6図に示す構造が多く採用されているのである。
In each of these cases, for positive bevel, the depletion layer when voltage is applied is on the 18 side (high resistivity side), and for negative bevel, the depletion layer when voltage is applied is on the PB side (low resistivity side), respectively. The negative In case of bevel,
Compared to the case of a positive bevel, since the angle 0 is extremely small, the area around the urinary ridge that must be reserved for the bevel structure inevitably becomes larger, which is disadvantageous in terms of effective utilization of the wafer. In addition, in the case of a negative bevel, the bevel angle θ must be further reduced as the withstand voltage becomes higher, which is disadvantageous when compared to the case of a positive bevel in terms of control of the same angle θ. Therefore, in order to increase the voltage resistance and improve the effective utilization rate of the wafer, conventionally, even if there is only one J2 junction, the positive hevel shown in Figs. 5 and 6 has been conventionally used. Many structures are used.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

またこへで通常の場合、大容量、高耐圧の半導体素子に
は1円形チップを用いたメサ形構造が採用され、前記ポ
ジティブベベル形状を得るためには、チップを回転させ
なからウエノ\端面に研摩材粉末を吹き付けて、対象部
分を研削するようにした。いわゆるサンドブラスト加工
が常用されており、このサンドブラスト加工によって研
削されたシリコン形状は、プラストノズルから噴出され
る研摩材粉末の密度分布に大きく依存する。
In addition, normally, a mesa-shaped structure using a circular chip is adopted for large-capacity, high-voltage semiconductor devices, and in order to obtain the positive bevel shape, the chip must be rotated and The target area was ground by spraying abrasive powder on it. So-called sandblasting is commonly used, and the shape of silicon ground by this sandblasting largely depends on the density distribution of the abrasive powder ejected from the blast nozzle.

第7図はこの従来例での半導体装置製造過程におけるサ
ンドブラスト時のチップ端面形状の部分拡大図で、8は
そのプラストノズル、矢印は噴出される研摩材粉末の流
線を示し、第8図は第7図に一ニ線部分での研摩材粉末
の密度分布を示している。
FIG. 7 is a partially enlarged view of the chip end shape during sandblasting in the semiconductor device manufacturing process in this conventional example, where 8 indicates the blast nozzle, arrows indicate streamlines of the abrasive powder being ejected, and FIG. FIG. 7 shows the density distribution of the abrasive powder in one line.

すなわち、シリコン研削加工に際して、研摩材粉末は、
第8図に示す密度分布、第7図に示す流線に依存してプ
ラストされるために、被加工部分としてのチップ端面形
状が、所期のポジティブベベル形状とならずに、同第7
図に見られる通り、外周稜角部分が丸味を帯びた形状に
なるもので、このためにJ2接合とウェハ端面とがなす
ベベル角度0が、所期のような鋭角にはならず、直角か
もしくは鈍角になって了うという不都合があり、またこ
の被加工端面形状は、前記のようにプラスト時の研摩材
粉末の密度分布、流線に大きく依存することから、プラ
ストノズル8の噴出方向角度の設定に影響されて再現性
に乏しく、端面形状の加工制御が極めて困難であるなど
の問題点を有し。
In other words, during silicon grinding, the abrasive powder is
Because the blasting depends on the density distribution shown in Figure 8 and the streamlines shown in Figure 7, the shape of the end face of the chip as the processed part does not become the expected positive bevel shape.
As seen in the figure, the outer periphery edge part has a rounded shape, so the bevel angle 0 between the J2 junction and the wafer edge is not as acute as expected, but is instead a right angle or There is an inconvenience that the end face ends up at an obtuse angle, and the shape of the end face to be machined depends largely on the density distribution and streamlines of the abrasive powder at the time of blasting, as described above, so the angle of the ejection direction of the blasting nozzle 8 is It has problems such as poor reproducibility due to the influence of settings, and extremely difficult processing control of the end face shape.

このような理由からこの種の半導体装置においては、耐
電圧特性が不安定になり、漏れ電流が大きくなる傾向に
あった。なお、第9図の曲線りは従来例によるこのよう
な半導体素子でのオフ状態特性を示している。
For these reasons, in this type of semiconductor device, the withstand voltage characteristics tend to become unstable and leakage current tends to increase. Incidentally, the curved line in FIG. 9 shows the off-state characteristics of such a conventional semiconductor element.

この発明は、従来のこのような問題点を改善するために
なされたもので、その目的とするところは、−ウェハ端
面に研摩材粉末を吹き付けて研削加工するようにした装
置構成において、良好かつ効果的なポジティブへベル形
状を形成し得るようにした半導体装置を提供することで
ある。
This invention was made in order to improve these conventional problems, and its purpose is to: - provide a good and efficient grinding process in an apparatus configuration that performs grinding by spraying abrasive powder onto the end face of a wafer; An object of the present invention is to provide a semiconductor device capable of forming an effective positive heel shape.

〔問題点を解決するための手段〕 この発明に係る半導体装置は、半導体基板の外周部に対
して、この外周部を研摩材粉末の吹き付け衝突から保護
する保護膜を形成させたものである。
[Means for Solving the Problems] A semiconductor device according to the present invention has a protective film formed on the outer periphery of a semiconductor substrate to protect the outer periphery from being bombarded with abrasive powder.

〔作   用〕[For production]

従ってこの発明においては、半導体基板の外周部に保護
膜を形成させた〜めに、サンドプラスト時に保護膜下の
シリコンにダメージを与えることがなく、また吹き付け
られる研摩材粉末の実質的な密度分布を、被加工端面の
稜角部から急激に立」一つだ理想的なものにできて、鋭
角的な研削加工をなし得られ、かつ加工形状の再現性を
向」二できる。
Therefore, in this invention, since a protective film is formed on the outer periphery of the semiconductor substrate, the silicon under the protective film is not damaged during sandplasting, and the abrasive powder that is sprayed has a substantial density distribution. It is possible to ideally create a sharply rising edge from the edge of the end face to be machined, thereby making it possible to perform sharp grinding and improve the reproducibility of the machined shape.

〔実 施 例〕〔Example〕

以下、この発明に係る半導体装置の実施例につき、第1
図ないし第4図を参照して詳細に説明する。
Hereinafter, the first embodiment of the semiconductor device according to the present invention will be described.
This will be explained in detail with reference to the drawings to FIG.

第1図および第2図はこの発明の第1および第2実施例
を適用した半導体装置の概要構成を示す断面模式図であ
り、これらの第1および第2実施例各図において前記従
来例各図と同一符号は同一または相当部分を示している
1 and 2 are schematic cross-sectional views showing the general structure of a semiconductor device to which the first and second embodiments of the present invention are applied. The same reference numerals as in the figures indicate the same or corresponding parts.

まず第1図に示す第1実施例は、外周ゲートタイプによ
る逆導通サイリスタに適用した場合であり、この第1実
施例構造においては、前記半導体基板1での第2の主面
の全外周部にあって、前記ゲート電極4とは分離された
全外周面を覆うように、酸化膜6を介して、例えば法着
、スパッタ。
First, the first embodiment shown in FIG. 1 is applied to a peripheral gate type reverse conduction thyristor. In this case, the oxide film 6 is formed by, for example, deposition or sputtering, so as to cover the entire outer peripheral surface separated from the gate electrode 4.

メンキなどの手段により、保護lり7を形成したもので
ある。
A protective layer 7 is formed by a method such as a coating.

こ\で前記保XCf Ii!、! 7の材質としては、
研摩材粉末を用いたサンドブラスト研削加工に際し、半
導体基板1面のシリコンに比較して研削加工速度が充分
に遅く、シリコン上に直接、あるいは酸化膜6を介して
形成し得る必要があり、金属、特に軟質金−屈が好適し
、例えば金(Au) 、銀(Ag) 、アルミニウム(
A l ) 、M (G:u)などで充分に目的を達成
できるもので、またその厚さとしては、 5IL〜30
g程度が適切であり、3ル以下では殆んど効果のないこ
とが判明した。
This is the above-mentioned Ho XCf Ii! ,! As for the material of 7,
When performing sandblast grinding using abrasive powder, the grinding speed must be sufficiently slow compared to the silicon on one side of the semiconductor substrate, and it must be possible to form the abrasive directly on the silicon or through the oxide film 6. Particularly suitable are soft metals such as gold (Au), silver (Ag), aluminum (
Al), M (G:u), etc. can fully achieve the purpose, and the thickness is 5IL to 30
It has been found that approximately 3 g is appropriate, and that less than 3 l has almost no effect.

また第2図に示す第2実施例は、センターゲートタイプ
による逆導通サイリスタに適用した場合であり、この第
2実施例構造の場合には、前記保護膜7をカソード電極
3に連接させることも可能である。
Further, the second embodiment shown in FIG. 2 is applied to a center gate type reverse conduction thyristor, and in the case of this second embodiment structure, the protective film 7 may be connected to the cathode electrode 3. It is possible.

しかしてこれらの各実施例構造を得るための。In order to obtain the structure of each of these embodiments.

製造過程における研摩材粉末を用いたサンドプラスI・
研削加工の態様を第3図に示し、また同上■−rv線部
分での研摩材粉末の密度分布を第4図に示しである。
Sand Plus I using abrasive powder in the manufacturing process
The mode of the grinding process is shown in FIG. 3, and the density distribution of the abrasive powder at the line 2-rv is shown in FIG. 4.

これらの各図から明らかなように、この実施例の場合に
は、サンドブラスト研削加工範囲に含まれて了うところ
の、チップ外周部が、保護膜7により覆われてブロック
されているために、サンドブラストに際してシリコンを
研削し得る研摩材粉末の密度分布は、実質的にこの保護
膜7によってブロックされた部分、つまり第4図での領
域Bを除いたものとなり、従ってチップ稜角該当部分で
の研摩材粉末の密度分布の立上りが急激で、このために
同チップ稜角部分を境界にして非常にシャープな研削加
工を行なうことができ、併せて保護膜7による保護のた
めに、サンドブラスト時にあって、チップ外周部にダメ
ージを与える惧れかない。
As is clear from these figures, in this example, the outer periphery of the chip, which is included in the sandblasting and grinding range, is covered and blocked by the protective film 7. The density distribution of the abrasive powder that can grind silicon during sandblasting is the one that excludes the area blocked by the protective film 7, that is, the area B in FIG. The density distribution of the material powder has a sharp rise, which makes it possible to perform very sharp grinding using the edge of the chip as a boundary.At the same time, due to the protection provided by the protective film 7, during sandblasting, There is no risk of damaging the outer periphery of the chip.

のってこのようにして加工形成されたチップ端面形状は
、第3図の通り極めて良好な鋭角状を呈し、かつまた前
記のように研摩材粉末の密度分布の切れがシャープ化さ
れるために、一方ではへベル角度θの制御形成が可能、
かつ容易になり、高精度の端面成形をなし得るのである
。因に第9図の曲線Cはこの実施例による半導体素子で
のオフ状態特性を示しており、曲線〕による従来例に比
較して、リーク電流の少ない良好なオフ状態特性を得る
ことができるのである。
The shape of the end face of the chip processed and formed in this manner exhibits an extremely good acute angle shape as shown in Fig. 3, and also because the edges of the density distribution of the abrasive powder are sharpened as described above. , on the other hand, it is possible to control the hevel angle θ,
Moreover, it is easy to form the end face with high precision. Incidentally, curve C in FIG. 9 shows the off-state characteristics of the semiconductor device according to this embodiment, and compared to the conventional example using curve C, it is possible to obtain better off-state characteristics with less leakage current. be.

なお、前記実施例においては、この発明を逆導通サイリ
スタに適用する場合について述べたが、その他、J2接
合をポジティブベベル構造とするサイリスタとか、ゲー
トターンオフサイリスタ、トランジスタなどの、高耐圧
半導体装置の全般に亘って適用できることは勿論である
In the above embodiments, the case where the present invention is applied to a reverse conduction thyristor has been described, but it is also applicable to general high-voltage semiconductor devices such as thyristors whose J2 junction has a positive bevel structure, gate turn-off thyristors, and transistors. Of course, it can be applied to

〔発明の効果〕〔Effect of the invention〕

以上詳述したようにこの発明によれば、半導体基板の外
周部に保護膜を形成させた−めに、ベベル構造成形のた
めの、研摩材粉末によるサンドブラスト時にあって、保
護膜下のシリコンにダメージを与える惧れがなく、また
吹き付けられる研摩材粉末の実質的な密度分布を、被加
工チップ端面の稜角部から急激に立上った理想的なもの
にできて、鋭角的な研削加工を高精度に制御性良くなし
得ると共に、加工形状の再現性を向」二でき、しかも構
造的にも簡単で容易に実施し得るなどの優れた特長を有
するものである。
As detailed above, according to the present invention, in order to form a protective film on the outer periphery of a semiconductor substrate, during sandblasting with abrasive powder for forming a bevel structure, the silicon under the protective film is There is no risk of damage, and the actual density distribution of the sprayed abrasive powder can be made ideal, rising sharply from the edge of the edge of the chip to be processed, making it possible to grind sharp edges. It has excellent features such as being able to perform the process with high precision and good controllability, improving the reproducibility of the machined shape, and being structurally simple and easy to implement.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図はこの発明の第1および第2実施例
を適用した半導体装置の概要構成を示すそれぞれ断面模
式図、第3図は同上製造過程における研摩材粉末による
サンドブラスト研削加工の態様を示す部分拡大図、第4
図は同上第3図TV−■線部分での研摩材粉末の密度分
布を示す説明図であり、また第5図および第6図は従来
例による半導体装置の概要構成を各別に示すそれぞれ断
面模式図、第7図は同上製造過程における研摩材粉末に
よるサンドブラスト研削加工の態様を示す部分拡大図、
第8図は同上節7図■−■線部分での研摩材粉末の密度
分布を示す説明図、第9図は実施例と従来例との半導体
装置のオフ状態特性図である。 1・・・・半導体基板、2・・・・アノード電極板、3
・・・・カソード電極、4・・・・ゲート電極、8・・
・・酸化膜、7・・・・保護膜。 代理人  大  岩  増  雄 薄*キ甑− 第5図 第6図 第7図 第8図 甲/p +
1 and 2 are schematic cross-sectional views showing the general structure of a semiconductor device to which the first and second embodiments of the present invention are applied, and FIG. 3 is a mode of sandblasting grinding using abrasive powder in the manufacturing process of the same. Partially enlarged view showing 4th
The figure is an explanatory diagram showing the density distribution of the abrasive powder at the TV-■ line section in Figure 3, and Figures 5 and 6 are cross-sectional schematic diagrams showing the general structure of a conventional semiconductor device. Figure 7 is a partially enlarged view showing the mode of sandblasting grinding using abrasive powder in the same manufacturing process;
FIG. 8 is an explanatory diagram showing the density distribution of the abrasive powder in the section 1--2 in FIG. 1... Semiconductor substrate, 2... Anode electrode plate, 3
...Cathode electrode, 4...Gate electrode, 8...
... Oxide film, 7... Protective film. Agent Masu Oiwa Yuusaku * Kiyoshi - Figure 5 Figure 6 Figure 7 Figure 8 A/p +

Claims (5)

【特許請求の範囲】[Claims] (1)少なくとも1つのpn接合と2つの主面をもつ半
導体基板、第1の主面上に鑞付けされた支持電極板、第
2の主面上に形成された電極を有し、前記第1の主面側
から第2の主面側にかけて漸時に断面積を大きくした半
導体装置において、前記半導体基板の第2の主面の外周
部に対し、同外周部を研摩材粉末の吹き付け衝突から保
護する保護膜を形成させたことを特徴とする半導体装置
(1) A semiconductor substrate having at least one pn junction and two main surfaces, a support electrode plate brazed on the first main surface, and an electrode formed on the second main surface; In a semiconductor device whose cross-sectional area gradually increases from the side of the first main surface to the side of the second main surface, the outer periphery of the second main surface of the semiconductor substrate is prevented from being bombarded with abrasive powder. A semiconductor device characterized by forming a protective film for protection.
(2)保護膜の材質が、金、銀、アルミニウム、銅など
の軟質金属であることを特徴とする特許請求の範囲第1
項記載の半導体装置。
(2) Claim 1, wherein the material of the protective film is a soft metal such as gold, silver, aluminum, or copper.
1. Semiconductor device described in Section 1.
(3)保護膜の厚さが、5μ〜30μであることを特徴
とする特許請求の範囲第1項、第2項のいずれかに記載
の半導体装置。
(3) The semiconductor device according to claim 1 or 2, wherein the protective film has a thickness of 5 μ to 30 μ.
(4)第2の主面の外周部に、酸化膜を介して保護膜を
形成させたことを特徴とする特許請求の範囲第1項、第
2項、第3項のいずれかに記載の半導体装置。
(4) A protective film is formed on the outer periphery of the second main surface via an oxide film. Semiconductor equipment.
(5)第2の主面の外周部にあつて、同主面上の電極と
は分離して保護膜を形成させたことを特徴とする特許請
求の範囲第1項、第2項、第3項、第4項のいずれかに
記載の半導体装置。
(5) Claims 1, 2 and 2, characterized in that a protective film is formed on the outer periphery of the second main surface, separate from the electrodes on the same main surface. The semiconductor device according to any one of Item 3 and Item 4.
JP17603785A 1985-08-08 1985-08-08 Semiconductor device Pending JPS6235568A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17603785A JPS6235568A (en) 1985-08-08 1985-08-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17603785A JPS6235568A (en) 1985-08-08 1985-08-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6235568A true JPS6235568A (en) 1987-02-16

Family

ID=16006615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17603785A Pending JPS6235568A (en) 1985-08-08 1985-08-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6235568A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100159699A1 (en) * 2008-12-19 2010-06-24 Yoshimi Takahashi Sandblast etching for through semiconductor vias

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49123778A (en) * 1973-03-31 1974-11-27
JPS54113275A (en) * 1978-02-24 1979-09-04 Toshiba Corp Semiconductor device
JPS5778170A (en) * 1980-10-31 1982-05-15 Toshiba Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49123778A (en) * 1973-03-31 1974-11-27
JPS54113275A (en) * 1978-02-24 1979-09-04 Toshiba Corp Semiconductor device
JPS5778170A (en) * 1980-10-31 1982-05-15 Toshiba Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100159699A1 (en) * 2008-12-19 2010-06-24 Yoshimi Takahashi Sandblast etching for through semiconductor vias

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