JPS60157257A - Processing method of end surface inclination for semiconductor element - Google Patents
Processing method of end surface inclination for semiconductor elementInfo
- Publication number
- JPS60157257A JPS60157257A JP1371784A JP1371784A JPS60157257A JP S60157257 A JPS60157257 A JP S60157257A JP 1371784 A JP1371784 A JP 1371784A JP 1371784 A JP1371784 A JP 1371784A JP S60157257 A JPS60157257 A JP S60157257A
- Authority
- JP
- Japan
- Prior art keywords
- angle
- grinding
- semiconductor element
- spraying
- abrasive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000003672 processing method Methods 0.000 title description 3
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000005507 spraying Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 21
- 239000000843 powder Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 23
- 229910052710 silicon Inorganic materials 0.000 description 23
- 239000010703 silicon Substances 0.000 description 23
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 8
- 229910052750 molybdenum Inorganic materials 0.000 description 8
- 239000011733 molybdenum Substances 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 239000003082 abrasive agent Substances 0.000 description 5
- 230000005684 electric field Effects 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3046—Mechanical treatment, e.g. grinding, polishing, cutting using blasting, e.g. sand-blasting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thyristors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、半導体基体の2つの主面のうち、支持基板
と接触する主面の面積が、他方の主面の面積よりも小さ
くなるようにするための半導体素子の端面傾斜付加工方
法に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] This invention provides a semiconductor substrate having two principal surfaces, such that the area of the principal surface in contact with the supporting substrate is smaller than the area of the other principal surface. The present invention relates to a method of processing a semiconductor element to provide a beveled end face.
pnpn構造の高耐圧大容量ゲートターンオフサイリス
タ(GTO)では、可制御電流の増大ケはかるために、
pベース領域の不純物濃度欠品くする必要があるので、
順方向耐圧を高耐圧化することが一般のサイリスタに比
べて難しい。逆方向耐圧については回路構成上必要とし
7ない場合か多い。この場合、順方向耐圧のみ欠品耐圧
化すれは良いので、順方向耐圧火阻止する接合ヶポジテ
ィブ・ベベル構造とし高耐圧化ケはかることが好ましい
。しかしながら、大電力半導体素子にお(・ては、一般
に機械的強度の増大やヒートザイクルによるストレスの
緩和ケはかるために、シリコン等からなる半導体基体に
モリブデンやタングステン等の支持基板をろう付してい
るので、シリコンウェハの上面と下面付近における物理
的な対称性が失なわれ、研削スピードが異なる。In order to increase the controllable current in a high-voltage, large-capacity gate turn-off thyristor (GTO) with a pnpn structure,
Since it is necessary to reduce the impurity concentration in the p base region,
It is difficult to increase the forward breakdown voltage compared to general thyristors. There are many cases where reverse breakdown voltage is not necessary due to the circuit configuration. In this case, since only the forward breakdown voltage can be increased to the stockout breakdown voltage, it is preferable to use a positive bevel structure for the joint to prevent forward breakdown voltage and to increase the breakdown voltage. However, in order to increase mechanical strength and alleviate stress caused by heat cycles in high-power semiconductor devices, a support substrate made of molybdenum or tungsten is generally brazed to a semiconductor substrate made of silicon or the like. As a result, the physical symmetry near the top and bottom surfaces of the silicon wafer is lost, resulting in different grinding speeds.
第1図(a)、(b)は従来の端面研削方法を示す説明
図であり、1は半導体基体(以下シリコンウェハという
)、2は支持基板(以下モリブデン板という)で、両者
で半導体素子が形成されている。FIGS. 1(a) and 1(b) are explanatory diagrams showing a conventional end face grinding method, in which 1 is a semiconductor substrate (hereinafter referred to as a silicon wafer), 2 is a support substrate (hereinafter referred to as a molybdenum plate), and both of them are used to form a semiconductor element. is formed.
3は研摩材吹き付は用のノズル、4は半導体素子を回転
するための回転治具である。なお、矢印は研摩材の流れ
ケ示す。以下、製造工程について説明する。3 is a nozzle for spraying abrasive material, and 4 is a rotating jig for rotating the semiconductor element. Note that the arrows indicate the flow of the abrasive material. The manufacturing process will be explained below.
まず、シリコンウェハ12.モリブデン板2からなる半
導体素子タシリコンウェ′ハ1の面ケ上にして、回転治
具4に挿入し回転させながら半導体素子の外周から回転
中心Oに向って、研摩材吹き付ζす用のノズル3かも、
研摩材を噴出させてシリコンウェハ1の端面な傾斜付加
工するものである。First, silicon wafer 12. A semiconductor element made of a molybdenum plate 2 is placed on the surface of a silicon wafer 1, and the abrasive material is sprayed from the outer periphery of the semiconductor element toward the rotation center O while the semiconductor element is inserted into a rotating jig 4 and rotated. Maybe nozzle 3.
The end surface of the silicon wafer 1 is beveled by jetting an abrasive material.
ところが、上記のような方法では、研摩材の吹き付(す
方向と、被研摩面のなす角度θ、が小さいために、研摩
材の吹き付は方向に対してシリコンウェハ1の上側と下
側の研削スピードが著しく異なること、およびシリコン
ウェハIK比べてモリブデン板2の研削スピードが著し
く小さいためにモリブデン板20面からの研摩材の反射
の影響によって、シリコンウェハ1の下面付近の研削ス
ピードが著しく大きくなること等により、所望の傾斜角
度が得られ難いという欠点があった。すなわち、端面形
状の時間的推移を示す第2図(a) 、 (b) 。However, in the above method, since the angle θ between the direction in which the abrasive is sprayed and the surface to be polished is small, the abrasive is sprayed on the upper and lower sides of the silicon wafer 1 in the direction. Because the grinding speed of the molybdenum plate 2 is significantly different from that of the silicon wafer IK, and because the grinding speed of the molybdenum plate 2 is significantly lower than that of the silicon wafer IK, the grinding speed near the bottom surface of the silicon wafer 1 is significantly lower due to the reflection of the abrasive from the surface of the molybdenum plate 20. There was a drawback that it was difficult to obtain a desired inclination angle due to the increase in size, etc. In other words, FIGS. 2(a) and 2(b) show the time course of the end face shape.
(e)かられかるように、J22食近辺の傾斜角度θ2
が大きすぎる反面、シリコンウェハ1の下面においては
1食い込みdが大きいため表面電界の均一性が失われ、
良好な耐電圧特性が得られないという欠点があった。(e) As you can see, the inclination angle θ2 near the J22 eclipse
On the other hand, on the bottom surface of the silicon wafer 1, the 1 bite d is large, so the uniformity of the surface electric field is lost.
There was a drawback that good withstand voltage characteristics could not be obtained.
この発明は、上記のような従来のものの欠点を除去する
ためになされたもので、研摩材の吹き付は方向と被研摩
面とをほぼ直角にすることにより吹き付は方向に対して
シリコンウェハの上側と下側の研削スピードヶ同一にし
、角度形成の制御精度を向上する半導体素子の端面傾斜
付加工方法を提供するものである。This invention was made in order to eliminate the above-mentioned drawbacks of the conventional ones.The direction of the abrasive spray is made almost perpendicular to the surface to be polished. The present invention provides a method for machining an end face of a semiconductor device with an inclined end face, in which the grinding speed on the upper and lower sides of the semiconductor device is made the same, and the control accuracy of angle formation is improved.
第3図(&)〜(d)はこの発明の一実施例を示す端面
研削方法の工程説明図である。この図で、1〜4は第1
図と同一のものを示し、5は前記シリコンウェハ1を研
削する砥石である。FIGS. 3(&) to 3(d) are process explanatory diagrams of an end face grinding method showing an embodiment of the present invention. In this figure, 1 to 4 are the first
The same thing as in the figure is shown, and 5 is a grindstone for grinding the silicon wafer 1.
この実施例では、まず、第3図(a)に示すように、シ
リコンウェハ1.モリブデン板2からなる半導体素子を
シリコンウェハ10面を上にして、回転治具4に挿入し
、シリコンウェハ1の上面の面積が下面の面積よりも小
さくなるように砥石5により第3図(b)のように研削
する。この研削角度は、最終的なシリコンクエバ1の端
面傾斜角度lcc+o’v加えた角度に対して研摩材の
吹き付は角度θ、と、研削後のシリコンウェハ1の傾斜
角度の差Δθを減じた角度θ、に設定することが好まし
い。この後、第3図(b)の工程で形成された研削面に
対して第3図(c)のように直角に研摩材火吹き付ける
。この場合、吹き付は方向に対してシリコンクエバ1の
上側と下側の研削スピードがほぼ同一となるため、順方
向電圧を阻止する接合J、(第4図参照)付近のシリコ
ン傾斜角度θ。In this embodiment, first, as shown in FIG. 3(a), a silicon wafer 1. A semiconductor element made of a molybdenum plate 2 is inserted into a rotating jig 4 with the silicon wafer 10 side facing up, and a grindstone 5 is used so that the area of the upper surface of the silicon wafer 1 is smaller than the area of the lower surface as shown in FIG. 3 (b). ) to grind. This grinding angle is an angle obtained by subtracting the difference Δθ between the inclination angles of the silicon wafer 1 after grinding and the angle θ at which the abrasive is sprayed with respect to the final end face inclination angle lcc + o'v of the silicon wafer 1. It is preferable to set it to θ. Thereafter, as shown in FIG. 3(c), an abrasive material is sprayed at right angles to the ground surface formed in the step of FIG. 3(b). In this case, since the grinding speed of the upper and lower sides of the silicon cube 1 is almost the same in the direction of spraying, the silicon inclination angle θ near the junction J (see FIG. 4) that blocks forward voltage.
の制御か容易となり、その精度も向上する。これを第3
図(d)に示す。This makes it easier to control and improves its accuracy. This is the third
Shown in Figure (d).
例えば、目標とするポンディプベベル角度′1に60゜
とすると、第3図(b)の工程の研削角度θ3はシリコ
ンウェハ1の主面に対して60°+90°−15゜=1
35°とし、第3図(e)の工程の研削についてはノズ
ル3の吹き付は角度θ、の設定値760°−15°=4
5°とする。なお、第3図(b)、(c)の各工程にお
けるシリコンウェハ1の端面の研削形状の時間的推移は
第4図(a)、(b)に示される。For example, if the target pump dip bevel angle '1 is 60 degrees, the grinding angle θ3 in the step of FIG. 3(b) is 60 degrees + 90 degrees - 15 degrees = 1
35°, and for the grinding process in Fig. 3(e), the spray angle of the nozzle 3 is set at the angle θ, 760° - 15° = 4
Set to 5°. Incidentally, the time course of the grinding shape of the end face of the silicon wafer 1 in each step of FIGS. 3(b) and 3(c) is shown in FIGS. 4(a) and 4(b).
この図かられかるように、順方向電圧ケ阻止する接合J
2付近の傾斜角度を容易、かつ精度良く制御でき、また
、研削時間も短くできるので、シリコンウェハ1の下面
ケ余分に削ることがなくなり。As can be seen from this figure, the junction J that blocks the forward voltage
Since the inclination angle around 2 can be easily and accurately controlled and the grinding time can be shortened, the lower surface of the silicon wafer 1 does not need to be ground excessively.
研削後の形状は鋭く、きわめて良好になる。The shape after grinding is sharp and very good.
以上説明したよ5K、この発明は半導体基体と支持基板
とを有する半導体素子の半導体基体の下面が上面の面積
よりも太き(なるように半導体素子の端面を傾斜面に加
工する工程と、形IN、された傾斜面に対してほぼ直角
に研摩材粉末ケ半導体基体に吹き付けながら研削”する
工程とを有するので、順方向電圧を阻止する接合面付近
のシリコンウェハの傾斜角度の制御が容易となり、その
精度か向上する。また、表面電界分布を均一化すること
が可能であるため、良好な耐電圧特性を得ることができ
る等の利点な有する。As explained above, the present invention includes a step of processing the end face of the semiconductor element into an inclined surface so that the lower surface of the semiconductor element of a semiconductor element having a semiconductor substrate and a supporting substrate is thicker than the area of the upper surface, and This process involves the process of "grinding" the semiconductor substrate while spraying the abrasive powder almost perpendicularly to the inclined surface, which facilitates control of the inclination angle of the silicon wafer near the bonding surface to block forward voltage. In addition, since it is possible to make the surface electric field distribution uniform, it has advantages such as good withstand voltage characteristics.
第1図(、)、(b)は従来の端面研削方法を示す説明
図、第2図(a) 、(b) 、(c)は端面形状の時
間的推移を示す図、第3図(a)〜(d)はこの発明の
一実施例を示す端面研削方法の工程説明図、第4図(a
)、(b)は第3図の実施例における端面形状の時間的
推移ケ示す図である。
図中、1はシリコンウェハ、2はモリブデン板、3はノ
ズル、4は回転治具、5は砥石である。
なお、図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 (外2名ン
第1図
(a)
(b)
第2図
(a) (a
(b)
第3図
第4図
(a)
手続補正書(自発)
特許庁長官殿
1、事件の表示 特願昭59−013717号2、発明
の名称 半導体素子の端面傾斜付加工方法3、補正をす
る者
5、補正の対象
明細書の特許請求の範囲の欄9発明の詳細な説明の欄お
よび図面
6、補正の内容
+11 明細書の特許請求の範囲を別紙のように補正す
る。
(2) 同じく第6頁1行の1ポンチイブベベル」を、
「ポジティブベベル」と補正する。
(3)図面第3図(b)の符号1を別紙未配のよ5に補
正する。
以上
2、特許請求の範囲
少なくとも2つの主面を持つ半導体基体の前記一方の主
面が支持基板にろう付けされた半導体素子におい【、前
記半導体基体の2つの主面のうち前記支持基板に接触す
る主面の面積が他の主面の面積よりも小さくなるように
前記半導体基体の端面な傾斜付加工するに際して、前記
半導体基体の2つの主面のうち前記支持基板に接触する
面積を他方の主面よりも大きくなるように研削する工程
と、この工程により形成された端面の傾斜面に対してほ
ぼ直角に研摩材粉末を吹き付けながら研削する工程とを
含むことを特徴とする半導体素子の端面傾斜付加工方法
。Figures 1 (, ) and (b) are explanatory diagrams showing the conventional end face grinding method, Figures 2 (a), (b) and (c) are diagrams showing the time course of the end face shape, and Figure 3 ( a) to (d) are process explanatory diagrams of an end face grinding method showing one embodiment of the present invention, and FIG.
) and (b) are diagrams showing the time course of the end face shape in the embodiment of FIG. 3. In the figure, 1 is a silicon wafer, 2 is a molybdenum plate, 3 is a nozzle, 4 is a rotating jig, and 5 is a grindstone. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 (a) (b) Figure 2 (a) (a (b) Figure 3 Figure 4 (a) Procedural amendment (voluntary) Dear Commissioner of the Japan Patent Office 1. Indication of the case Japanese Patent Application No. 59-013717 2. Title of the invention 3. Processing method for tilting the end face of a semiconductor device 3. Person making the amendment 5. Claims column 9 of the specification to be amended 9. Details of the invention Explanation column, drawing 6, content of amendment + 11 The claims of the specification are amended as shown in the attached sheet.
Correct as "positive bevel". (3) Correct the code 1 in Figure 3(b) to 5 as the attached sheet has not been distributed. Above 2, claims include a semiconductor element in which the one main surface of a semiconductor substrate having at least two main surfaces is brazed to a support substrate; When processing the end face of the semiconductor substrate to be inclined so that the area of the main surface is smaller than the area of the other main surfaces, the area of the two main surfaces of the semiconductor substrate that contacts the support substrate is An end face of a semiconductor element comprising: a step of grinding the end face to be larger than the main face; and a step of grinding while spraying abrasive powder substantially perpendicularly to the inclined surface of the end face formed by this step. Beveled processing method.
Claims (1)
面が支持基板にろう付けされた半導体素子において、前
記半導体基体の2つの主面のうち前記支持基板に接触す
る主面の面積が他の主面の面積よりも小さくなるように
前記半導体基体の端面を傾斜付加工するに際して、前記
半導体基体の2つの主面のうち前記支持基板に接触する
面積を他方の主面よりも大きくする工程と、この工程に
より形成された端面の傾斜面に対してほぼ直角に研摩材
粉末を吹き付けながら研削する工程と7含むことを特徴
とする半導体素子の端面傾斜付加工方法。In a semiconductor element in which one main surface of a semiconductor substrate having at least two main surfaces is brazed to a support substrate, the area of the main surface in contact with the support substrate among the two main surfaces of the semiconductor substrate is larger than the other main surface. a step of making an area of the two main surfaces of the semiconductor substrate that contacts the supporting substrate larger than the other main surface when processing the end surface of the semiconductor substrate to be inclined so that the end surface is smaller than the area of the main surface; 7. A method for processing a semiconductor element with an inclined end surface, comprising the steps of: 7. Grinding while spraying abrasive powder substantially perpendicularly to the inclined surface of the end surface formed in this step.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1371784A JPS60157257A (en) | 1984-01-25 | 1984-01-25 | Processing method of end surface inclination for semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1371784A JPS60157257A (en) | 1984-01-25 | 1984-01-25 | Processing method of end surface inclination for semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60157257A true JPS60157257A (en) | 1985-08-17 |
Family
ID=11840991
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1371784A Pending JPS60157257A (en) | 1984-01-25 | 1984-01-25 | Processing method of end surface inclination for semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60157257A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4822757A (en) * | 1987-11-10 | 1989-04-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
EP0320090A2 (en) * | 1987-12-10 | 1989-06-14 | Westinghouse Brake And Signal Holdings Limited | Shaping silicon semiconductor wafers |
JP2011142216A (en) * | 2010-01-07 | 2011-07-21 | Nano System Solutions:Kk | Wafer edge and wafer reverse surface processing device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4942199A (en) * | 1972-08-26 | 1974-04-20 | ||
JPS5383A (en) * | 1976-06-24 | 1978-01-05 | Mitsubishi Electric Corp | Semiconductor device |
-
1984
- 1984-01-25 JP JP1371784A patent/JPS60157257A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4942199A (en) * | 1972-08-26 | 1974-04-20 | ||
JPS5383A (en) * | 1976-06-24 | 1978-01-05 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4822757A (en) * | 1987-11-10 | 1989-04-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
EP0320090A2 (en) * | 1987-12-10 | 1989-06-14 | Westinghouse Brake And Signal Holdings Limited | Shaping silicon semiconductor wafers |
JP2011142216A (en) * | 2010-01-07 | 2011-07-21 | Nano System Solutions:Kk | Wafer edge and wafer reverse surface processing device |
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