JPS54159831A - Adder and subtractor for numbers different in data length using counter circuit - Google Patents

Adder and subtractor for numbers different in data length using counter circuit

Info

Publication number
JPS54159831A
JPS54159831A JP6870178A JP6870178A JPS54159831A JP S54159831 A JPS54159831 A JP S54159831A JP 6870178 A JP6870178 A JP 6870178A JP 6870178 A JP6870178 A JP 6870178A JP S54159831 A JPS54159831 A JP S54159831A
Authority
JP
Japan
Prior art keywords
circuit
data
adder
subtractor
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6870178A
Other languages
English (en)
Other versions
JPS5728128B2 (ja
Inventor
Katsuyuki Iwata
Takashi Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6870178A priority Critical patent/JPS54159831A/ja
Publication of JPS54159831A publication Critical patent/JPS54159831A/ja
Publication of JPS5728128B2 publication Critical patent/JPS5728128B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/3816—Accepting numbers of variable word length
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/481—Counters performing arithmetic operations
JP6870178A 1978-06-07 1978-06-07 Adder and subtractor for numbers different in data length using counter circuit Granted JPS54159831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6870178A JPS54159831A (en) 1978-06-07 1978-06-07 Adder and subtractor for numbers different in data length using counter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6870178A JPS54159831A (en) 1978-06-07 1978-06-07 Adder and subtractor for numbers different in data length using counter circuit

Publications (2)

Publication Number Publication Date
JPS54159831A true JPS54159831A (en) 1979-12-18
JPS5728128B2 JPS5728128B2 (ja) 1982-06-15

Family

ID=13381325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6870178A Granted JPS54159831A (en) 1978-06-07 1978-06-07 Adder and subtractor for numbers different in data length using counter circuit

Country Status (1)

Country Link
JP (1) JPS54159831A (ja)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5537689A (en) * 1978-09-05 1980-03-15 Motorola Inc Carry*anticipator circuit
JPS56147047A (en) * 1980-04-18 1981-11-14 Hitachi Ltd Bit division type adder
JPS58182754A (ja) * 1982-04-19 1983-10-25 Hitachi Ltd 演算処理装置
JPS60189311A (ja) * 1984-03-08 1985-09-26 Sony Corp デイジタル信号処理装置
JPS617945A (ja) * 1984-06-22 1986-01-14 Usac Electronics Ind Co Ltd 実効アドレス計算方式
JPS61109141A (ja) * 1984-10-31 1986-05-27 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション ２進増分器
JPS61250733A (ja) * 1985-04-30 1986-11-07 Fujitsu Ltd 加減算回路
JPS61267873A (ja) * 1985-05-23 1986-11-27 Fuji Xerox Co Ltd デ−タ処理装置
JPS62111362A (ja) * 1985-11-08 1987-05-22 Matsushita Electric Ind Co Ltd デ−タ処理装置
JPS62269228A (ja) * 1986-05-16 1987-11-21 Matsushita Electric Ind Co Ltd 算術論理演算ユニツト
JPS6491228A (en) * 1987-09-30 1989-04-10 Takeshi Sakamura Data processor
JPH05216624A (ja) * 1992-02-03 1993-08-27 Mitsubishi Electric Corp 演算装置

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5537689A (en) * 1978-09-05 1980-03-15 Motorola Inc Carry*anticipator circuit
JPS56147047A (en) * 1980-04-18 1981-11-14 Hitachi Ltd Bit division type adder
JPS6227412B2 (ja) * 1982-04-19 1987-06-15 Hitachi Ltd
JPS58182754A (ja) * 1982-04-19 1983-10-25 Hitachi Ltd 演算処理装置
JPS60189311A (ja) * 1984-03-08 1985-09-26 Sony Corp デイジタル信号処理装置
JPS617945A (ja) * 1984-06-22 1986-01-14 Usac Electronics Ind Co Ltd 実効アドレス計算方式
JPS61109141A (ja) * 1984-10-31 1986-05-27 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション ２進増分器
JPH0379736B2 (ja) * 1984-10-31 1991-12-19 Intaanashonaru Bijinesu Mashiinzu Corp
JPS61250733A (ja) * 1985-04-30 1986-11-07 Fujitsu Ltd 加減算回路
JPS61267873A (ja) * 1985-05-23 1986-11-27 Fuji Xerox Co Ltd デ−タ処理装置
JPS62111362A (ja) * 1985-11-08 1987-05-22 Matsushita Electric Ind Co Ltd デ−タ処理装置
JPS62269228A (ja) * 1986-05-16 1987-11-21 Matsushita Electric Ind Co Ltd 算術論理演算ユニツト
JPS6491228A (en) * 1987-09-30 1989-04-10 Takeshi Sakamura Data processor
JPH05216624A (ja) * 1992-02-03 1993-08-27 Mitsubishi Electric Corp 演算装置

Also Published As

Publication number Publication date
JPS5728128B2 (ja) 1982-06-15

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