JPS54158876A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS54158876A
JPS54158876A JP6856178A JP6856178A JPS54158876A JP S54158876 A JPS54158876 A JP S54158876A JP 6856178 A JP6856178 A JP 6856178A JP 6856178 A JP6856178 A JP 6856178A JP S54158876 A JPS54158876 A JP S54158876A
Authority
JP
Japan
Prior art keywords
type
region
electrode
collector
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6856178A
Other languages
Japanese (ja)
Inventor
Mitsuharu Morishita
Shiro Iwatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6856178A priority Critical patent/JPS54158876A/en
Publication of JPS54158876A publication Critical patent/JPS54158876A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: To make a chip size small on the whole with no need for epitaxial grown by forming several N+-type collector regions in a P-type semiconductor substrate by diffusion and then by providing a P+-type base region and a N+-type emitter region in it.
CONSTITUTION: When an IC is constituted by forming two PNP-type transistors in a P+-type semiconductor substrate, N+-type collector region 20 is formed by selective diffusion in P+-type semiconductor substrate 1 first. Next, P+-type base region 6 in region 20 and N+-type emitter region 7 in it are provided sequentially by selective diffusion, and collector electrode 9, base electrode 10, and emitter electrode 11 are respectively fitted to regions 20, 6 and 7. Then, substrate electrode 12 is bonded to both entire sides of substrate 1. In this way, no epitaxial layer is provided to an IC which requires no so high reverse dielectric strength between the base and collector, thereby constituting the device in an extremely-simple process.
COPYRIGHT: (C)1979,JPO&Japio
JP6856178A 1978-06-06 1978-06-06 Manufacture of semiconductor device Pending JPS54158876A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6856178A JPS54158876A (en) 1978-06-06 1978-06-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6856178A JPS54158876A (en) 1978-06-06 1978-06-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS54158876A true JPS54158876A (en) 1979-12-15

Family

ID=13377290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6856178A Pending JPS54158876A (en) 1978-06-06 1978-06-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS54158876A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5022582A (en) * 1973-05-25 1975-03-11

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5022582A (en) * 1973-05-25 1975-03-11

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