JPS5413263A - Electrode forming method for semiconductor element - Google Patents

Electrode forming method for semiconductor element

Info

Publication number
JPS5413263A
JPS5413263A JP7788677A JP7788677A JPS5413263A JP S5413263 A JPS5413263 A JP S5413263A JP 7788677 A JP7788677 A JP 7788677A JP 7788677 A JP7788677 A JP 7788677A JP S5413263 A JPS5413263 A JP S5413263A
Authority
JP
Japan
Prior art keywords
semiconductor element
forming method
electrode forming
resist
enable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7788677A
Other languages
Japanese (ja)
Inventor
Ryosaku Kanzawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7788677A priority Critical patent/JPS5413263A/en
Publication of JPS5413263A publication Critical patent/JPS5413263A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To enable to manufacture small pad distance simply, by forming solder film with vacuum evaporation through the use of metallic mask after coating the IC element surface other than soldering film forming region with the plated resist such as photo resist.
COPYRIGHT: (C)1979,JPO&Japio
JP7788677A 1977-07-01 1977-07-01 Electrode forming method for semiconductor element Pending JPS5413263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7788677A JPS5413263A (en) 1977-07-01 1977-07-01 Electrode forming method for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7788677A JPS5413263A (en) 1977-07-01 1977-07-01 Electrode forming method for semiconductor element

Publications (1)

Publication Number Publication Date
JPS5413263A true JPS5413263A (en) 1979-01-31

Family

ID=13646545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7788677A Pending JPS5413263A (en) 1977-07-01 1977-07-01 Electrode forming method for semiconductor element

Country Status (1)

Country Link
JP (1) JPS5413263A (en)

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