JPH1186561A5 - - Google Patents

Info

Publication number
JPH1186561A5
JPH1186561A5 JP1998195181A JP19518198A JPH1186561A5 JP H1186561 A5 JPH1186561 A5 JP H1186561A5 JP 1998195181 A JP1998195181 A JP 1998195181A JP 19518198 A JP19518198 A JP 19518198A JP H1186561 A5 JPH1186561 A5 JP H1186561A5
Authority
JP
Japan
Prior art keywords
bit line
bit lines
input
coupled
stored value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP1998195181A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1186561A (ja
Filing date
Publication date
Priority claimed from US08/891,173 external-priority patent/US5815432A/en
Application filed filed Critical
Publication of JPH1186561A publication Critical patent/JPH1186561A/ja
Publication of JPH1186561A5 publication Critical patent/JPH1186561A5/ja
Withdrawn legal-status Critical Current

Links

JP10195181A 1997-07-10 1998-07-10 シングルエンド読み取りデュアルエンド書き込みｓｒａｍセル Withdrawn JPH1186561A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US891173 1997-07-10
US08/891,173 US5815432A (en) 1997-07-10 1997-07-10 Single-ended read, dual-ended write SCRAM cell

Publications (2)

Publication Number Publication Date
JPH1186561A JPH1186561A (ja) 1999-03-30
JPH1186561A5 true JPH1186561A5 (enExample) 2005-10-20

Family

ID=25397742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10195181A Withdrawn JPH1186561A (ja) 1997-07-10 1998-07-10 シングルエンド読み取りデュアルエンド書き込みｓｒａｍセル

Country Status (4)

Country Link
US (1) US5815432A (enExample)
EP (1) EP0890954B1 (enExample)
JP (1) JPH1186561A (enExample)
DE (1) DE69835399T2 (enExample)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6046930A (en) * 1998-09-01 2000-04-04 International Business Machines Corporation Memory array and method for writing data to memory
US6166946A (en) * 2000-01-21 2000-12-26 Hewlett-Packard Company System and method for writing to and reading from a memory cell
JP2002056681A (ja) * 2000-08-09 2002-02-22 Toshiba Corp メモリ装置
US6560160B1 (en) 2000-11-13 2003-05-06 Agilent Technologies, Inc. Multi-port memory that sequences port accesses
US6501688B2 (en) 2001-05-30 2002-12-31 Micron Technology, Inc. tRCD margin
US6737685B2 (en) 2002-01-11 2004-05-18 International Business Machines Corporation Compact SRAM cell layout for implementing one-port or two-port operation
JP3520283B2 (ja) 2002-04-16 2004-04-19 沖電気工業株式会社 半導体記憶装置
US20040013946A1 (en) 2002-07-15 2004-01-22 Ube Industries, Ltd. Non-aqueous electrolytic solution and lithium battery
US6838723B2 (en) 2002-08-29 2005-01-04 Micron Technology, Inc. Merged MOS-bipolar capacitor memory cell
US7224024B2 (en) * 2002-08-29 2007-05-29 Micron Technology, Inc. Single transistor vertical memory gain cell
US20040090820A1 (en) * 2002-11-08 2004-05-13 Saroj Pathak Low standby power SRAM
US6804142B2 (en) * 2002-11-12 2004-10-12 Micron Technology, Inc. 6F2 3-transistor DRAM gain cell
US7030436B2 (en) * 2002-12-04 2006-04-18 Micron Technology, Inc. Embedded DRAM gain memory cell having MOS transistor body provided with a bi-polar transistor charge injecting means
JP4167127B2 (ja) 2003-05-29 2008-10-15 沖電気工業株式会社 半導体集積装置
JP4186768B2 (ja) * 2003-09-16 2008-11-26 沖電気工業株式会社 マルチポート半導体メモリ
US7403640B2 (en) * 2003-10-27 2008-07-22 Hewlett-Packard Development Company, L.P. System and method for employing an object-oriented motion detector to capture images
US7242609B2 (en) * 2005-09-01 2007-07-10 Sony Computer Entertainment Inc. Methods and apparatus for low power SRAM
US7545670B2 (en) * 2007-07-10 2009-06-09 Sony Computer Entertainment Inc. Dual word line or floating bit line low power SRAM
US20130141997A1 (en) * 2011-12-06 2013-06-06 International Business Machines Corporation Single-ended volatile memory access
US20130141992A1 (en) 2011-12-06 2013-06-06 International Business Machines Corporation Volatile memory access via shared bitlines
US8817562B2 (en) * 2012-07-31 2014-08-26 Freescale Semiconductor, Inc. Devices and methods for controlling memory cell pre-charge operations
US20140104960A1 (en) * 2012-10-15 2014-04-17 Sundar Iyer Methods and Apparatus for Designing and Constructing High-Speed Memory Circuits
US9542995B2 (en) * 2013-08-30 2017-01-10 Manoj Sachdev Threshold voltage mismatch compensation sense-amplifiers for static random access memories with multiple differential inputs
US11011222B2 (en) * 2019-03-06 2021-05-18 Arm Limited Memory structure with bitline strapping
US11955169B2 (en) 2021-03-23 2024-04-09 Qualcomm Incorporated High-speed multi-port memory supporting collision
US11764764B1 (en) * 2022-09-13 2023-09-19 Nanya Technology Corporation Latch device and operation method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3992703A (en) * 1974-10-09 1976-11-16 Rockwell International Corporation Memory output circuit
US5034923A (en) * 1987-09-10 1991-07-23 Motorola, Inc. Static RAM with soft defect detection
EP0473819A1 (en) * 1990-09-05 1992-03-11 International Business Machines Corporation Multiport memory cell
JP3357382B2 (ja) * 1991-05-28 2002-12-16 株式会社日立製作所 多ポートメモリ
US5642325A (en) * 1995-09-27 1997-06-24 Philips Electronics North America Corporation Register file read/write cell
US5699292A (en) * 1996-01-04 1997-12-16 Micron Technology, Inc. SRAM cell employing substantially vertically elongated pull-up resistors

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