JPH1174344A - 半導体デバイスの製造方法 - Google Patents

半導体デバイスの製造方法

Info

Publication number
JPH1174344A
JPH1174344A JP10178739A JP17873998A JPH1174344A JP H1174344 A JPH1174344 A JP H1174344A JP 10178739 A JP10178739 A JP 10178739A JP 17873998 A JP17873998 A JP 17873998A JP H1174344 A JPH1174344 A JP H1174344A
Authority
JP
Japan
Prior art keywords
trench
silicon
layer
silicon oxide
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10178739A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1174344A5 (enExample
Inventor
Norbert Arnold
アルノルト ノルベルト
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of JPH1174344A publication Critical patent/JPH1174344A/ja
Publication of JPH1174344A5 publication Critical patent/JPH1174344A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
JP10178739A 1997-06-26 1998-06-25 半導体デバイスの製造方法 Withdrawn JPH1174344A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/883,356 US5783476A (en) 1997-06-26 1997-06-26 Integrated circuit devices including shallow trench isolation
US08/883356 1997-06-26

Publications (2)

Publication Number Publication Date
JPH1174344A true JPH1174344A (ja) 1999-03-16
JPH1174344A5 JPH1174344A5 (enExample) 2005-09-15

Family

ID=25382434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10178739A Withdrawn JPH1174344A (ja) 1997-06-26 1998-06-25 半導体デバイスの製造方法

Country Status (6)

Country Link
US (1) US5783476A (enExample)
EP (1) EP0887855A1 (enExample)
JP (1) JPH1174344A (enExample)
KR (1) KR100540850B1 (enExample)
CN (1) CN1133208C (enExample)
TW (1) TW393722B (enExample)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100226488B1 (ko) * 1996-12-26 1999-10-15 김영환 반도체 소자 격리구조 및 그 형성방법
US6133123A (en) 1997-08-21 2000-10-17 Micron Technology, Inc. Fabrication of semiconductor gettering structures by ion implantation
KR100275730B1 (ko) * 1998-05-11 2000-12-15 윤종용 트렌치 소자분리 방법
US6093619A (en) * 1998-06-18 2000-07-25 Taiwan Semiconductor Manufaturing Company Method to form trench-free buried contact in process with STI technology
US6355540B2 (en) * 1998-07-27 2002-03-12 Acer Semicondutor Manufacturing Inc. Stress-free shallow trench isolation
US6054364A (en) * 1998-09-08 2000-04-25 Advanced Micro Devices Chemical mechanical polishing etch stop for trench isolation
US6071794A (en) * 1999-06-01 2000-06-06 Mosel Vitelic, Inc. Method to prevent the formation of a thinner portion of insulating layer at the junction between the side walls and the bottom insulator
US6309937B1 (en) * 1999-05-03 2001-10-30 Vlsi Technology, Inc. Method of making shallow junction semiconductor devices
TW415017B (en) * 1999-08-11 2000-12-11 Mosel Vitelic Inc Method of improving trench isolation
US6350659B1 (en) 1999-09-01 2002-02-26 Agere Systems Guardian Corp. Process of making semiconductor device having regions of insulating material formed in a semiconductor substrate
US6187650B1 (en) * 1999-11-05 2001-02-13 Promos Tech., Inc. Method for improving global planarization uniformity of a silicon nitride layer used in the formation of trenches by using a sandwich stop layer
US6348395B1 (en) * 2000-06-07 2002-02-19 International Business Machines Corporation Diamond as a polish-stop layer for chemical-mechanical planarization in a damascene process flow
US6680239B1 (en) * 2000-07-24 2004-01-20 Chartered Semiconductor Manufacturing Ltd. Effective isolation with high aspect ratio shallow trench isolation and oxygen or field implant
US6432798B1 (en) * 2000-08-10 2002-08-13 Intel Corporation Extension of shallow trench isolation by ion implantation
US6437417B1 (en) * 2000-08-16 2002-08-20 Micron Technology, Inc. Method for making shallow trenches for isolation
TW521377B (en) * 2000-08-29 2003-02-21 Agere Syst Guardian Corp Trench structure and method of corner rounding
US6524929B1 (en) 2001-02-26 2003-02-25 Advanced Micro Devices, Inc. Method for shallow trench isolation using passivation material for trench bottom liner
US6486038B1 (en) 2001-03-12 2002-11-26 Advanced Micro Devices Method for and device having STI using partial etch trench bottom liner
US6521510B1 (en) 2001-03-23 2003-02-18 Advanced Micro Devices, Inc. Method for shallow trench isolation with removal of strained island edges
US6583488B1 (en) 2001-03-26 2003-06-24 Advanced Micro Devices, Inc. Low density, tensile stress reducing material for STI trench fill
US6534379B1 (en) 2001-03-26 2003-03-18 Advanced Micro Devices, Inc. Linerless shallow trench isolation method
KR20030056217A (ko) * 2001-12-27 2003-07-04 동부전자 주식회사 반도체 섭스트레이트의 소자 분리 방법
US6576558B1 (en) * 2002-10-02 2003-06-10 Taiwan Semiconductor Manufacturing Company High aspect ratio shallow trench using silicon implanted oxide
JP2004280493A (ja) * 2003-03-17 2004-10-07 Sanyo Electric Co Ltd 半導体素子のレイアウト設計装置、レイアウト設計方法及びレイアウト設計プログラム
JP2005142319A (ja) * 2003-11-06 2005-06-02 Renesas Technology Corp 半導体装置の製造方法
KR100571410B1 (ko) * 2003-12-31 2006-04-14 동부아남반도체 주식회사 반도체 소자의 트랜치 소자 분리막 형성 방법
US20060063338A1 (en) * 2004-09-20 2006-03-23 Lsi Logic Corporation Shallow trench isolation depth extension using oxygen implantation
CN100416793C (zh) * 2005-11-24 2008-09-03 上海华虹Nec电子有限公司 应用于浅沟槽隔离工艺中改善器件隔离效果的方法
KR100822469B1 (ko) 2005-12-07 2008-04-16 삼성전자주식회사 복수개의 소자를 상호 격리시키기 위한 에어캐비티를구비한 시스템 온 칩 구조물, 듀플렉서, 및 그 제조 방법
US20070158779A1 (en) * 2006-01-12 2007-07-12 International Business Machines Corporation Methods and semiconductor structures for latch-up suppression using a buried damage layer
US7648869B2 (en) * 2006-01-12 2010-01-19 International Business Machines Corporation Method of fabricating semiconductor structures for latch-up suppression
US7491618B2 (en) * 2006-01-26 2009-02-17 International Business Machines Corporation Methods and semiconductor structures for latch-up suppression using a conductive region
US7276768B2 (en) * 2006-01-26 2007-10-02 International Business Machines Corporation Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures
US20070194403A1 (en) * 2006-02-23 2007-08-23 International Business Machines Corporation Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods
US8112817B2 (en) * 2006-10-30 2012-02-07 Girish Chiruvolu User-centric authentication system and method
KR100845102B1 (ko) * 2006-12-20 2008-07-09 동부일렉트로닉스 주식회사 반도체 소자의 소자분리막 형성방법
US7818702B2 (en) * 2007-02-28 2010-10-19 International Business Machines Corporation Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates
US7754513B2 (en) * 2007-02-28 2010-07-13 International Business Machines Corporation Latch-up resistant semiconductor structures on hybrid substrates and methods for forming such semiconductor structures
US8299633B2 (en) * 2009-12-21 2012-10-30 Advanced Micro Devices, Inc. Semiconductor chip device with solder diffusion protection
US8956948B2 (en) * 2010-05-20 2015-02-17 Globalfoundries Inc. Shallow trench isolation extension
US8399957B2 (en) 2011-04-08 2013-03-19 International Business Machines Corporation Dual-depth self-aligned isolation structure for a back gate electrode
US20130043513A1 (en) 2011-08-19 2013-02-21 United Microelectronics Corporation Shallow trench isolation structure and fabricating method thereof
JP6238234B2 (ja) * 2014-06-03 2017-11-29 ルネサスエレクトロニクス株式会社 半導体装置
US10522549B2 (en) * 2018-02-17 2019-12-31 Varian Semiconductor Equipment Associates, Inc. Uniform gate dielectric for DRAM device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4842675A (en) * 1986-07-07 1989-06-27 Texas Instruments Incorporated Integrated circuit isolation process
JPH01281747A (ja) * 1988-05-09 1989-11-13 Nec Corp 絶縁膜埋込みトレンチの形成方法
JPH01295438A (ja) * 1988-05-24 1989-11-29 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US5183775A (en) * 1990-01-23 1993-02-02 Applied Materials, Inc. Method for forming capacitor in trench of semiconductor wafer by implantation of trench surfaces with oxygen
JPH0437152A (ja) * 1990-06-01 1992-02-07 Fujitsu Ltd 半導体装置の製造方法
GB9410874D0 (en) * 1994-05-31 1994-07-20 Inmos Ltd Semiconductor device incorporating an isolating trench and manufacture thereof
US5393693A (en) * 1994-06-06 1995-02-28 United Microelectronics Corporation "Bird-beak-less" field isolation method
US5565376A (en) * 1994-07-12 1996-10-15 United Microelectronics Corp. Device isolation technology by liquid phase deposition
US5445989A (en) * 1994-08-23 1995-08-29 United Microelectronics Corp. Method of forming device isolation regions
KR0186083B1 (ko) * 1995-08-12 1999-04-15 문정환 반도체 소자의 소자격리방법

Also Published As

Publication number Publication date
US5783476A (en) 1998-07-21
KR100540850B1 (ko) 2006-02-28
TW393722B (en) 2000-06-11
CN1133208C (zh) 2003-12-31
CN1204148A (zh) 1999-01-06
KR19990007123A (ko) 1999-01-25
EP0887855A1 (en) 1998-12-30

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