JPH11503565A - 集積回路装置を収容するための部品 - Google Patents

集積回路装置を収容するための部品

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Publication number
JPH11503565A
JPH11503565A JP8529426A JP52942696A JPH11503565A JP H11503565 A JPH11503565 A JP H11503565A JP 8529426 A JP8529426 A JP 8529426A JP 52942696 A JP52942696 A JP 52942696A JP H11503565 A JPH11503565 A JP H11503565A
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JP
Japan
Prior art keywords
component
package
circuit lines
metal
metal substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8529426A
Other languages
English (en)
Japanese (ja)
Inventor
アール． ホフマン，ポール
マフリカル，デーパク
エイ． ブラスウェイト，ジョージ
ソロモン，ダウィット
パルタサラティ，アルビンド
Original Assignee
オリン コーポレイション
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Publication date
Application filed by オリン コーポレイション filed Critical オリン コーポレイション
Publication of JPH11503565A publication Critical patent/JPH11503565A/ja
Pending legal-status Critical Current

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    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Dispersion Chemistry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
JP8529426A 1995-03-29 1996-03-11 集積回路装置を収容するための部品 Pending JPH11503565A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US413,149 1989-09-27
US41314995A 1995-03-29 1995-03-29
PCT/US1996/003258 WO1996030942A1 (en) 1995-03-29 1996-03-11 Components for housing an integrated circuit device

Publications (1)

Publication Number Publication Date
JPH11503565A true JPH11503565A (ja) 1999-03-26

Family

ID=23636049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8529426A Pending JPH11503565A (ja) 1995-03-29 1996-03-11 集積回路装置を収容するための部品

Country Status (4)

Country Link
JP (1) JPH11503565A (enrdf_load_stackoverflow)
AU (1) AU5360496A (enrdf_load_stackoverflow)
TW (1) TW309654B (enrdf_load_stackoverflow)
WO (1) WO1996030942A1 (enrdf_load_stackoverflow)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005002335A (ja) * 2003-05-21 2005-01-06 Japan Gore Tex Inc 接着フィルムおよびこれを使った半導体装置
JP2010528491A (ja) * 2007-05-25 2010-08-19 エレクトロ サイエンティフィック インダストリーズ インコーポレーテッド 絶縁された導電性接点を金属パッケージを貫通するように形成するプロセス
JP2010245337A (ja) * 2009-04-07 2010-10-28 Elpida Memory Inc 半導体装置及びその製造方法
JP2013077765A (ja) * 2011-09-30 2013-04-25 Sumitomo Electric Device Innovations Inc 半導体装置
KR101381438B1 (ko) * 2010-04-30 2014-04-04 유보틱 인텔릭츄얼 프라퍼티 컴퍼니 리미티드 인쇄회로기판에 전기적으로 결합되도록 구성된 에어 캐비티 패키지 및 상기 에어 캐비티 패키지의 제공 방법

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6946728B2 (en) 2004-02-19 2005-09-20 Hewlett-Packard Development Company, L.P. System and methods for hermetic sealing of post media-filled MEMS package
JP4387269B2 (ja) * 2004-08-23 2009-12-16 株式会社テクニスコ ビアが形成されたガラス基板及びビアの形成方法
US9930793B2 (en) * 2014-03-27 2018-03-27 Intel Corporation Electric circuit on flexible substrate
US9392713B2 (en) * 2014-10-17 2016-07-12 Rsm Electron Power, Inc. Low cost high strength surface mount package
US11444048B2 (en) 2017-10-05 2022-09-13 Texas Instruments Incorporated Shaped interconnect bumps in semiconductor devices

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136348A (ja) * 1983-12-26 1985-07-19 Hitachi Ltd 半導体装置
JPS6298737A (ja) * 1985-10-25 1987-05-08 Sharp Corp 半導体装置の交換方法
US4888449A (en) * 1988-01-04 1989-12-19 Olin Corporation Semiconductor package
US4897508A (en) * 1988-02-10 1990-01-30 Olin Corporation Metal electronic package
JPH0260149A (ja) * 1988-08-26 1990-02-28 Matsushita Electric Works Ltd 半導体パッケージ
US4939316A (en) * 1988-10-05 1990-07-03 Olin Corporation Aluminum alloy semiconductor packages
US4968552A (en) * 1989-10-13 1990-11-06 International Business Machines Corp. Versatile reactive ion etch barriers from polyamic acid salts
JPH04216655A (ja) * 1990-12-18 1992-08-06 Nec Kyushu Ltd 半導体装置
US5352926A (en) * 1993-01-04 1994-10-04 Motorola, Inc. Flip chip package and method of making

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005002335A (ja) * 2003-05-21 2005-01-06 Japan Gore Tex Inc 接着フィルムおよびこれを使った半導体装置
JP2010528491A (ja) * 2007-05-25 2010-08-19 エレクトロ サイエンティフィック インダストリーズ インコーポレーテッド 絶縁された導電性接点を金属パッケージを貫通するように形成するプロセス
JP2010245337A (ja) * 2009-04-07 2010-10-28 Elpida Memory Inc 半導体装置及びその製造方法
KR101381438B1 (ko) * 2010-04-30 2014-04-04 유보틱 인텔릭츄얼 프라퍼티 컴퍼니 리미티드 인쇄회로기판에 전기적으로 결합되도록 구성된 에어 캐비티 패키지 및 상기 에어 캐비티 패키지의 제공 방법
JP2013077765A (ja) * 2011-09-30 2013-04-25 Sumitomo Electric Device Innovations Inc 半導体装置

Also Published As

Publication number Publication date
TW309654B (enrdf_load_stackoverflow) 1997-07-01
WO1996030942A1 (en) 1996-10-03
AU5360496A (en) 1996-10-16

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