JPH11330422A5 - - Google Patents

Info

Publication number
JPH11330422A5
JPH11330422A5 JP1999082088A JP8208899A JPH11330422A5 JP H11330422 A5 JPH11330422 A5 JP H11330422A5 JP 1999082088 A JP1999082088 A JP 1999082088A JP 8208899 A JP8208899 A JP 8208899A JP H11330422 A5 JPH11330422 A5 JP H11330422A5
Authority
JP
Japan
Prior art keywords
layer
semiconductor device
word line
vertical
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1999082088A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11330422A (ja
JP5175010B2 (ja
Filing date
Publication date
Priority claimed from US09/047,581 external-priority patent/US6172390B1/en
Application filed filed Critical
Publication of JPH11330422A publication Critical patent/JPH11330422A/ja
Publication of JPH11330422A5 publication Critical patent/JPH11330422A5/ja
Application granted granted Critical
Publication of JP5175010B2 publication Critical patent/JP5175010B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP08208899A 1998-03-25 1999-03-25 ダイナミックランダムアクセスメモリ、ダイナミックランダムアクセスメモリのアレイ、およびｄｒａｍデバイス Expired - Fee Related JP5175010B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/047,581 US6172390B1 (en) 1998-03-25 1998-03-25 Semiconductor device with vertical transistor and buried word line
US09/047581 1998-03-25

Publications (3)

Publication Number Publication Date
JPH11330422A JPH11330422A (ja) 1999-11-30
JPH11330422A5 true JPH11330422A5 (https=) 2006-02-23
JP5175010B2 JP5175010B2 (ja) 2013-04-03

Family

ID=21949806

Family Applications (1)

Application Number Title Priority Date Filing Date
JP08208899A Expired - Fee Related JP5175010B2 (ja) 1998-03-25 1999-03-25 ダイナミックランダムアクセスメモリ、ダイナミックランダムアクセスメモリのアレイ、およびｄｒａｍデバイス

Country Status (6)

Country Link
US (1) US6172390B1 (https=)
EP (1) EP0948053B1 (https=)
JP (1) JP5175010B2 (https=)
KR (1) KR100643425B1 (https=)
CN (1) CN1197161C (https=)
TW (1) TW410463B (https=)

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DE10008814B4 (de) * 2000-02-25 2006-06-29 Mosel Vitelic Inc. Aufbau eines Drams mit vertikalem Transistor und dessen Herstellung
TW451425B (en) * 2000-05-16 2001-08-21 Nanya Technology Corp Manufacturing method for memory cell transistor
DE10028424C2 (de) * 2000-06-06 2002-09-19 Infineon Technologies Ag Herstellungsverfahren für DRAM-Speicherzellen
US6399447B1 (en) * 2000-07-19 2002-06-04 International Business Machines Corporation Method of producing dynamic random access memory (DRAM) cell with folded bitline vertical transistor
US6284593B1 (en) * 2000-11-03 2001-09-04 International Business Machines Corporation Method for shallow trench isolated, contacted well, vertical MOSFET DRAM
DE10111755C1 (de) * 2001-03-12 2002-05-16 Infineon Technologies Ag Verfahren zur Herstellung einer Speicherzelle eines Halbleiterspeichers
US6437388B1 (en) * 2001-05-25 2002-08-20 Infineon Technologies Ag Compact trench capacitor memory cell with body contact
US6610573B2 (en) * 2001-06-22 2003-08-26 Infineon Technologies Ag Method for forming a single wiring level for transistors with planar and vertical gates on the same substrate
TW506059B (en) * 2001-09-25 2002-10-11 Promos Techvologies Inc Forming method for shallow trench
US7224024B2 (en) * 2002-08-29 2007-05-29 Micron Technology, Inc. Single transistor vertical memory gain cell
US6838723B2 (en) * 2002-08-29 2005-01-04 Micron Technology, Inc. Merged MOS-bipolar capacitor memory cell
DE10243380A1 (de) * 2002-09-18 2004-04-01 Infineon Technologies Ag Verfahren zur Herstellung einer integrierten Halbleiterschaltung
US6804142B2 (en) * 2002-11-12 2004-10-12 Micron Technology, Inc. 6F2 3-transistor DRAM gain cell
US7030436B2 (en) 2002-12-04 2006-04-18 Micron Technology, Inc. Embedded DRAM gain memory cell having MOS transistor body provided with a bi-polar transistor charge injecting means
DE10257873B3 (de) * 2002-12-11 2004-06-17 Infineon Technologies Ag Dynamische Speicherzelle und Verfahren zur Herstellung derselben
US6727141B1 (en) * 2003-01-14 2004-04-27 International Business Machines Corporation DRAM having offset vertical transistors and method
US6956256B2 (en) * 2003-03-04 2005-10-18 Micron Technology Inc. Vertical gain cell
US6830968B1 (en) * 2003-07-16 2004-12-14 International Business Machines Corporation Simplified top oxide late process
US8518457B2 (en) * 2004-05-11 2013-08-27 Pulmonox Technologies Corporation Use of inhaled gaseous nitric oxide as a mucolytic agent or expectorant
DE102005034387A1 (de) * 2005-07-22 2007-02-08 Infineon Technologies Ag Trench-DRAM-Halbleiterspeicher mit reduziertem Leckstrom
DE102005035641B4 (de) * 2005-07-29 2010-11-25 Qimonda Ag Herstellungsverfahren für eine Speicherzellenanordnung mit gefalteter Bitleitungs-Anordnung und entsprechende Speicherzellenanordnung mit gefalteter Bitleitungs-Anordnung
US20080108212A1 (en) * 2006-10-19 2008-05-08 Atmel Corporation High voltage vertically oriented eeprom device
US7800093B2 (en) * 2007-02-01 2010-09-21 Qimonda North America Corp. Resistive memory including buried word lines
KR100972900B1 (ko) * 2007-12-31 2010-07-28 주식회사 하이닉스반도체 반도체 소자 및 그 제조 방법
KR101024771B1 (ko) 2008-12-24 2011-03-24 주식회사 하이닉스반도체 매립 워드라인을 갖는 반도체 소자 및 그 제조 방법
US7948027B1 (en) * 2009-12-10 2011-05-24 Nanya Technology Corp. Embedded bit line structure, field effect transistor structure with the same and method of fabricating the same
KR101139987B1 (ko) * 2010-07-15 2012-05-02 에스케이하이닉스 주식회사 반도체 소자 및 그 제조 방법
TWI553782B (zh) * 2014-04-30 2016-10-11 華邦電子股份有限公司 埋入式字元線及其隔離結構的製造方法
CN105097641B (zh) * 2014-05-09 2017-11-07 华邦电子股份有限公司 埋入式字线及其隔离结构的制造方法
CN109830480B (zh) * 2017-11-23 2022-02-18 联华电子股份有限公司 动态随机存取存储器
US10770585B2 (en) 2018-09-24 2020-09-08 Globalfoundries Inc. Self-aligned buried contact for vertical field-effect transistor and method of production thereof

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US4824793A (en) 1984-09-27 1989-04-25 Texas Instruments Incorporated Method of making DRAM cell with trench capacitor
US5225697A (en) 1984-09-27 1993-07-06 Texas Instruments, Incorporated dRAM cell and method
US5102817A (en) 1985-03-21 1992-04-07 Texas Instruments Incorporated Vertical DRAM cell and method
US5164917A (en) 1985-06-26 1992-11-17 Texas Instruments Incorporated Vertical one-transistor DRAM with enhanced capacitance and process for fabricating
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JPS63107061A (ja) * 1986-10-23 1988-05-12 Toshiba Corp 半導体記憶装置の製造方法
US4833516A (en) 1987-08-03 1989-05-23 International Business Machines Corporation High density memory cell structure having a vertical trench transistor self-aligned with a vertical trench capacitor and fabrication methods therefor
US4949138A (en) * 1987-10-27 1990-08-14 Texas Instruments Incorporated Semiconductor integrated circuit device
US5227660A (en) * 1987-11-09 1993-07-13 Hitachi, Ltd. Semiconductor device
JP2606857B2 (ja) * 1987-12-10 1997-05-07 株式会社日立製作所 半導体記憶装置の製造方法
US5103276A (en) * 1988-06-01 1992-04-07 Texas Instruments Incorporated High performance composed pillar dram cell
JPH0214563A (ja) * 1988-07-01 1990-01-18 Matsushita Electron Corp 半導体記憶装置
US5252845A (en) 1990-04-02 1993-10-12 Electronics And Telecommunications Research Institute Trench DRAM cell with vertical transistor
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JPH0775247B2 (ja) * 1990-05-28 1995-08-09 株式会社東芝 半導体記憶装置
US5214603A (en) * 1991-08-05 1993-05-25 International Business Machines Corporation Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors
JPH0590534A (ja) * 1991-09-27 1993-04-09 Fujitsu Ltd 半導体装置及びその製造方法
US5208172A (en) 1992-03-02 1993-05-04 Motorola, Inc. Method for forming a raised vertical transistor
US5256588A (en) 1992-03-23 1993-10-26 Motorola, Inc. Method for forming a transistor and a capacitor for use in a vertically stacked dynamic random access memory cell
JPH05291528A (ja) * 1992-04-09 1993-11-05 Toshiba Corp 半導体記憶装置およびその製造方法
US5448513A (en) * 1993-12-02 1995-09-05 Regents Of The University Of California Capacitorless DRAM device on silicon-on-insulator substrate
KR960016773B1 (en) 1994-03-28 1996-12-20 Samsung Electronics Co Ltd Buried bit line and cylindrical gate cell and forming method thereof
US5529944A (en) * 1995-02-02 1996-06-25 International Business Machines Corporation Method of making cross point four square folded bitline trench DRAM cell
DE19519159C2 (de) * 1995-05-24 1998-07-09 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
DE19519160C1 (de) 1995-05-24 1996-09-12 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
US5885864A (en) 1996-10-24 1999-03-23 Micron Technology, Inc. Method for forming compact memory cell using vertical devices
US5929477A (en) 1997-01-22 1999-07-27 International Business Machines Corporation Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array
US5909618A (en) 1997-07-08 1999-06-01 Micron Technology, Inc. Method of making memory cell with vertical transistor and buried word and body lines
US5907170A (en) 1997-10-06 1999-05-25 Micron Technology, Inc. Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
US5831301A (en) * 1998-01-28 1998-11-03 International Business Machines Corp. Trench storage dram cell including a step transfer device
US5949700A (en) 1998-05-26 1999-09-07 International Business Machines Corporation Five square vertical dynamic random access memory cell

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