JPH11167514A5 - - Google Patents

Info

Publication number
JPH11167514A5
JPH11167514A5 JP1998229070A JP22907098A JPH11167514A5 JP H11167514 A5 JPH11167514 A5 JP H11167514A5 JP 1998229070 A JP1998229070 A JP 1998229070A JP 22907098 A JP22907098 A JP 22907098A JP H11167514 A5 JPH11167514 A5 JP H11167514A5
Authority
JP
Japan
Prior art keywords
data
write
memory
buffer
queue
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1998229070A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11167514A (ja
Filing date
Publication date
Priority claimed from US08/910,847 external-priority patent/US6134638A/en
Application filed filed Critical
Publication of JPH11167514A publication Critical patent/JPH11167514A/ja
Publication of JPH11167514A5 publication Critical patent/JPH11167514A5/ja
Pending legal-status Critical Current

Links

JP10229070A 1997-08-13 1998-08-13 動作速度が異なるｄｒａｍに対処できるメモリ制御機能を備えたコンピュータ・システム Pending JPH11167514A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US910847 1997-08-13
US08/910,847 US6134638A (en) 1997-08-13 1997-08-13 Memory controller supporting DRAM circuits with different operating speeds

Publications (2)

Publication Number Publication Date
JPH11167514A JPH11167514A (ja) 1999-06-22
JPH11167514A5 true JPH11167514A5 (enExample) 2005-11-04

Family

ID=25429399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10229070A Pending JPH11167514A (ja) 1997-08-13 1998-08-13 動作速度が異なるｄｒａｍに対処できるメモリ制御機能を備えたコンピュータ・システム

Country Status (3)

Country Link
US (1) US6134638A (enExample)
EP (1) EP0897154A3 (enExample)
JP (1) JPH11167514A (enExample)

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