JPH11167514A - 動作速度が異なるｄｒａｍに対処できるメモリ制御機能を備えたコンピュータ・システム - Google Patents

動作速度が異なるｄｒａｍに対処できるメモリ制御機能を備えたコンピュータ・システム

Info

Publication number
JPH11167514A
JPH11167514A JP10229070A JP22907098A JPH11167514A JP H11167514 A JPH11167514 A JP H11167514A JP 10229070 A JP10229070 A JP 10229070A JP 22907098 A JP22907098 A JP 22907098A JP H11167514 A JPH11167514 A JP H11167514A
Authority
JP
Japan
Prior art keywords
memory
computer system
data
processor
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10229070A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11167514A5 (enExample
Inventor
Sompong P Olarig
サンポン・ピー・オラリグ
Christopher J Pettey
クリストファー・ジェイ・ペティ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Publication of JPH11167514A publication Critical patent/JPH11167514A/ja
Publication of JPH11167514A5 publication Critical patent/JPH11167514A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
JP10229070A 1997-08-13 1998-08-13 動作速度が異なるｄｒａｍに対処できるメモリ制御機能を備えたコンピュータ・システム Pending JPH11167514A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/910,847 US6134638A (en) 1997-08-13 1997-08-13 Memory controller supporting DRAM circuits with different operating speeds
US910847 1997-08-13

Publications (2)

Publication Number Publication Date
JPH11167514A true JPH11167514A (ja) 1999-06-22
JPH11167514A5 JPH11167514A5 (enExample) 2005-11-04

Family

ID=25429399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10229070A Pending JPH11167514A (ja) 1997-08-13 1998-08-13 動作速度が異なるｄｒａｍに対処できるメモリ制御機能を備えたコンピュータ・システム

Country Status (3)

Country Link
US (1) US6134638A (enExample)
EP (1) EP0897154A3 (enExample)
JP (1) JPH11167514A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008226211A (ja) * 2007-02-13 2008-09-25 Megachips Lsi Solutions Inc メモリコントローラ
JP2010113435A (ja) * 2008-11-05 2010-05-20 Sanyo Electric Co Ltd メモリアクセス装置

Families Citing this family (111)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3092557B2 (ja) * 1997-09-16 2000-09-25 日本電気株式会社 半導体記憶装置
AU9798798A (en) * 1997-10-10 1999-05-03 Rambus Incorporated Power control system for synchronous memory device
WO1999019805A1 (en) 1997-10-10 1999-04-22 Rambus Incorporated Method and apparatus for two step memory write operations
US6401167B1 (en) 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
US6330627B1 (en) 1998-01-20 2001-12-11 Kabushiki Kaisha Toshiba System for fast data transfer between memory modules and controller using two clock lines each having a go line portion and a return line portion
US6314527B1 (en) * 1998-03-05 2001-11-06 Micron Technology, Inc. Recovery of useful areas of partially defective synchronous memory components
US6154821A (en) * 1998-03-10 2000-11-28 Rambus Inc. Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
US6233389B1 (en) 1998-07-30 2001-05-15 Tivo, Inc. Multimedia time warping system
US7558472B2 (en) 2000-08-22 2009-07-07 Tivo Inc. Multimedia signal processing system
US6434684B1 (en) * 1998-09-03 2002-08-13 Micron Technology, Inc. Method and apparatus for coupling signals across different clock domains, and memory device and computer system using same
US6366989B1 (en) * 1998-09-17 2002-04-02 Sun Microsystems, Inc. Programmable memory controller
US6418518B1 (en) 1998-09-18 2002-07-09 National Semiconductor Corporation Decoupled address and data access to an SDRAM
US6456502B1 (en) * 1998-09-21 2002-09-24 Compaq Computer Corporation Integrated circuit device/circuit board connection apparatus
US6490638B1 (en) * 1999-08-23 2002-12-03 Advanced Micro Devices, Inc. General purpose bus with programmable timing
US6321282B1 (en) * 1999-10-19 2001-11-20 Rambus Inc. Apparatus and method for topography dependent signaling
FR2806236B1 (fr) * 2000-03-07 2003-07-11 Canon Kk Procede et dispositif de transfert d'un paquet de donnees dans un reseau de communication
TW522297B (en) * 2000-03-17 2003-03-01 Micro Star Int Co Ltd Automatic over-clock method for CPU
US6862689B2 (en) 2001-04-12 2005-03-01 Stratus Technologies Bermuda Ltd. Method and apparatus for managing session information
US7236489B1 (en) * 2000-04-27 2007-06-26 Mosaid Technologies, Inc. Port packet queuing
JP3457628B2 (ja) * 2000-05-19 2003-10-20 Ｎｅｃエレクトロニクス株式会社 Ｃｐｕシステムおよび周辺ｌｓｉ
CA2316590A1 (en) * 2000-08-23 2002-02-23 Celestica International Inc. System and method for using a synchronous device with an asynchronous memory controller
US6636955B1 (en) * 2000-08-31 2003-10-21 Hewlett-Packard Development Company, L.P. Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature
GB2372603A (en) * 2000-12-14 2002-08-28 Psion Digital Ltd Method of synchronising a digital component with a synchronous memory device at power up
US6948010B2 (en) 2000-12-20 2005-09-20 Stratus Technologies Bermuda Ltd. Method and apparatus for efficiently moving portions of a memory block
US6766413B2 (en) 2001-03-01 2004-07-20 Stratus Technologies Bermuda Ltd. Systems and methods for caching with file-level granularity
US6874102B2 (en) 2001-03-05 2005-03-29 Stratus Technologies Bermuda Ltd. Coordinated recalibration of high bandwidth memories in a multiprocessor computer
US20020144173A1 (en) * 2001-03-30 2002-10-03 Micron Technology, Inc. Serial presence detect driven memory clock control
US6763444B2 (en) 2001-05-08 2004-07-13 Micron Technology, Inc. Read/write timing calibration of a memory array using a row or a redundant row
US6661554B2 (en) * 2001-08-23 2003-12-09 Cyoptics (Israel) Ltd. Biasing of an electro-optical component
US6983354B2 (en) 2002-05-24 2006-01-03 Micron Technology, Inc. Memory device sequencer and method supporting multiple memory device clock speeds
US6643216B1 (en) * 2002-08-02 2003-11-04 Nanoamp Solutions, Inc Asynchronous queuing circuit for DRAM external RAS accesses
US6948043B2 (en) * 2002-08-12 2005-09-20 Hewlett-Packard Development Company, L.P. Management of a memory subsystem
US7142416B2 (en) 2002-12-20 2006-11-28 Hewlett-Packard Development Company, L.P. Method and apparatus for determining the physical configuration of a multi-component system
US20040181367A1 (en) * 2003-03-11 2004-09-16 Nguyen Minh H. Diagnostic display
US6865135B2 (en) * 2003-03-12 2005-03-08 Micron Technology, Inc. Multi-frequency synchronizing clock signal generator
US20040193763A1 (en) * 2003-03-28 2004-09-30 Fujitsu Limited Inter-bus communication interface device and data security device
US7330991B2 (en) * 2003-05-15 2008-02-12 Lsi Logic Corporation Method and/or apparatus for paging to a dynamic memory array
KR20050022798A (ko) * 2003-08-30 2005-03-08 주식회사 이즈텍 유전자 어휘 분류체계를 이용하여 바이오 칩을 분석하기위한 시스템 및 그 방법
US7225303B2 (en) * 2003-09-22 2007-05-29 Micron Technology, Inc. Method and apparatus for accessing a dynamic memory device by providing at least one of burst and latency information over at least one of redundant row and column address lines
US7127584B1 (en) * 2003-11-14 2006-10-24 Intel Corporation System and method for dynamic rank specific timing adjustments for double data rate (DDR) components
US7054987B1 (en) * 2003-12-19 2006-05-30 Nvidia Corporation Apparatus, system, and method for avoiding data writes that stall transactions in a bus interface
US8250295B2 (en) 2004-01-05 2012-08-21 Smart Modular Technologies, Inc. Multi-rank memory module that emulates a memory module having a different number of ranks
US7532537B2 (en) 2004-03-05 2009-05-12 Netlist, Inc. Memory module with a circuit providing load isolation and memory domain translation
US7916574B1 (en) 2004-03-05 2011-03-29 Netlist, Inc. Circuit providing load isolation and memory domain translation for memory module
US7289386B2 (en) 2004-03-05 2007-10-30 Netlist, Inc. Memory module decoder
US7180520B2 (en) * 2004-03-08 2007-02-20 Intel Corporation Queue partitioning mechanism
JP4616586B2 (ja) * 2004-06-30 2011-01-19 富士通株式会社 メモリ初期化制御装置
TWI253079B (en) * 2004-08-27 2006-04-11 Via Tech Inc Method for deciding parameters of dram
US7327612B2 (en) * 2005-01-31 2008-02-05 Hewlett-Packard Development Company, L.P. Method and apparatus for providing the proper voltage to a memory
US20060179183A1 (en) * 2005-02-09 2006-08-10 International Business Machines Corporation Single burst completion of multiple writes at buffered DIMMs
US20060277355A1 (en) * 2005-06-01 2006-12-07 Mark Ellsberry Capacity-expanding memory device
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US7590796B2 (en) 2006-07-31 2009-09-15 Metaram, Inc. System and method for power management in memory systems
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US7580312B2 (en) 2006-07-31 2009-08-25 Metaram, Inc. Power saving system and method for use with a plurality of memory circuits
US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
KR100714396B1 (ko) * 2005-07-18 2007-05-04 삼성전자주식회사 메모리의 처리속도를 향상시킨 컴퓨터 시스템
GB2444663B (en) 2005-09-02 2011-12-07 Metaram Inc Methods and apparatus of stacking drams
KR100660546B1 (ko) * 2005-11-10 2006-12-22 삼성전자주식회사 반도체 디스크 제어 장치
US20070147404A1 (en) * 2005-12-27 2007-06-28 Lucent Technologies, Inc. Method and apparatus for policing connections using a leaky bucket algorithm with token bucket queuing
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US8121237B2 (en) 2006-03-16 2012-02-21 Rambus Inc. Signaling system with adaptive timing calibration
US20080005385A1 (en) * 2006-06-30 2008-01-03 Seagate Technology Llc Passive mirroring through concurrent transfer of data to multiple target devices
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
KR100845525B1 (ko) * 2006-08-07 2008-07-10 삼성전자주식회사 메모리 카드 시스템, 그것의 데이터 전송 방법, 그리고반도체 메모리 장치
US7886122B2 (en) * 2006-08-22 2011-02-08 Qimonda North America Corp. Method and circuit for transmitting a memory clock signal
US8266405B2 (en) 2006-12-13 2012-09-11 Cypress Semiconductor Corporation Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock domain
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US8417870B2 (en) 2009-07-16 2013-04-09 Netlist, Inc. System and method of increasing addressable memory space on a memory board
US8516185B2 (en) 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
US8154901B1 (en) 2008-04-14 2012-04-10 Netlist, Inc. Circuit providing load isolation and noise reduction
DE202010017690U1 (de) 2009-06-09 2012-05-29 Google, Inc. Programmierung von Dimm-Abschlusswiderstandswerten
US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation
JP5570619B2 (ja) 2010-02-23 2014-08-13 ラムバス・インコーポレーテッド 異なるメモリ種類にアクセスする異なる速度での時分割多重化
US20120254500A1 (en) * 2011-03-28 2012-10-04 Byungcheol Cho System architecture based on ddr memory
US20120254501A1 (en) * 2011-03-28 2012-10-04 Byungcheol Cho System architecture based on flash memory
EP2783277A1 (en) * 2011-12-07 2014-10-01 Huawei Technologies Co., Ltd. Queuing apparatus
US9436634B2 (en) * 2013-03-14 2016-09-06 Seagate Technology Llc Enhanced queue management
PL3629123T3 (pl) 2013-07-27 2021-08-16 Netlist, Inc. Moduł pamięci z lokalną synchronizacją
US9225322B2 (en) 2013-12-17 2015-12-29 Micron Technology, Inc. Apparatuses and methods for providing clock signals
KR102344834B1 (ko) * 2014-09-24 2021-12-29 삼성전자주식회사 솔리드 스테이트 드라이브 및 이를 포함하는 컴퓨팅 시스템
US9990138B2 (en) * 2015-03-31 2018-06-05 Toshiba Memory Corporation Out of order SGL read sorting in a mixed system with PRP read or system that supports only SGL reads
US9697884B2 (en) 2015-10-08 2017-07-04 Rambus Inc. Variable width memory module supporting enhanced error detection and correction
KR20170111572A (ko) * 2016-03-29 2017-10-12 삼성전자주식회사 반도체 메모리 장치 및 이의 동작 방법
US10579517B2 (en) 2018-03-19 2020-03-03 Dell Products, Lp System and method for providing per channel frequency optimization in a double data rate memory system
US11461030B2 (en) * 2019-07-15 2022-10-04 Micron Technology, Inc. Transferring data between clock domains using pulses across a queue
GB202203061D0 (en) * 2022-03-04 2022-04-20 Nordic Semiconductor Asa Interface circuit portions

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4233390A (en) * 1979-07-20 1980-11-11 Polychrome Corporation Lithographic printing plate having dual photosensitive layering
AU545651B2 (en) * 1980-04-11 1985-07-25 Sony Corporation Charge transfer filter circuit
JP2531802B2 (ja) * 1989-09-28 1996-09-04 甲府日本電気株式会社 リクエストバッファ制御システム
JPH04137081A (ja) * 1990-09-28 1992-05-12 Fuji Photo Film Co Ltd Ｅｅｐｒｏｍを有するｉｃメモリカード
US5448715A (en) * 1992-07-29 1995-09-05 Hewlett-Packard Company Dual clock domain interface between CPU and memory bus
JP3077866B2 (ja) * 1993-11-18 2000-08-21 日本電気株式会社 メモリモジュール
US5630096A (en) * 1995-05-10 1997-05-13 Microunity Systems Engineering, Inc. Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order
KR0170723B1 (ko) * 1995-12-29 1999-03-30 김광호 단일 ras 신호에 의해 동시 동작이 가능한 이중 뱅크를 갖는 반도체 메모리 장치

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008226211A (ja) * 2007-02-13 2008-09-25 Megachips Lsi Solutions Inc メモリコントローラ
JP2010113435A (ja) * 2008-11-05 2010-05-20 Sanyo Electric Co Ltd メモリアクセス装置

Also Published As

Publication number Publication date
EP0897154A3 (en) 2000-02-02
US6134638A (en) 2000-10-17
EP0897154A2 (en) 1999-02-17

Similar Documents

Publication Publication Date Title
JPH11167514A (ja) 動作速度が異なるｄｒａｍに対処できるメモリ制御機能を備えたコンピュータ・システム
US5239639A (en) Efficient memory controller with an independent clock
US6553435B1 (en) DMA transfer method for a system including a single-chip processor with a processing core and a device interface in different clock domains
US5353423A (en) Memory controller for use with write-back cache system and multiple bus masters coupled to multiple buses
US5218686A (en) Combined synchronous and asynchronous memory controller
EP1046111B1 (en) Data transferring in source-synchronous and common clock protocols
US7822904B2 (en) Capturing read data
US5220651A (en) Cpu-bus controller for accomplishing transfer operations between a controller and devices coupled to an input/output bus
US5919254A (en) Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system
JP3403284B2 (ja) 情報処理システム及びその制御方法
US8145805B2 (en) Method for re-sequencing commands and data between a master and target devices utilizing parallel processing
JPH04230544A (ja) ダイナミックメモリシステムのタイミングを動的に設定するデータ処理装置
US5287457A (en) Computer system DMA transfer
US5897667A (en) Method and apparatus for transferring data received from a first bus in a non-burst manner to a second bus in a burst manner
US6321233B1 (en) Apparatus for controlling pipelined memory access requests
US5809549A (en) Burst SRAMs for use with a high speed clock
JPH0916282A (ja) クロック制御方式
US5768624A (en) Method and apparatus for employing ping-pong buffering with one level deep buffers for fast DRAM access
US5175826A (en) Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385
US6266723B1 (en) Method and system for optimizing of peripheral component interconnect PCI bus transfers
EP1015992B1 (en) Clocking scheme for digital signal processor system
JPH04350754A (ja) データチャンネルに対するインターフェースを含むワークステーションまたは類似のデータ処理システム
US5590316A (en) Clock doubler and smooth transfer circuit
US6292807B1 (en) Method for controlling pipelined memory access requests
KR100297895B1 (ko) 동기식 ｄｒａｍ-타입 메모리와 시스템 버스간의 데이터 전송을 제어하는 방법 및 장치

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050809

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050809

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080729

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080731

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20081031

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20081216

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20090511