JPH10241354A - 双方向転送型記憶装置及びメモリの入出力制御方法 - Google Patents

双方向転送型記憶装置及びメモリの入出力制御方法

Info

Publication number
JPH10241354A
JPH10241354A JP9037683A JP3768397A JPH10241354A JP H10241354 A JPH10241354 A JP H10241354A JP 9037683 A JP9037683 A JP 9037683A JP 3768397 A JP3768397 A JP 3768397A JP H10241354 A JPH10241354 A JP H10241354A
Authority
JP
Japan
Prior art keywords
address
value
data
memory
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9037683A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10241354A5 (cg-RX-API-DMAC7.html
Inventor
Masayuki Koyama
雅行 小山
Naohiro Kobayashi
直弘 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9037683A priority Critical patent/JPH10241354A/ja
Priority to US08/876,048 priority patent/US6067605A/en
Priority to KR1019970043250A priority patent/KR100262434B1/ko
Publication of JPH10241354A publication Critical patent/JPH10241354A/ja
Publication of JPH10241354A5 publication Critical patent/JPH10241354A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
    • G06F7/785—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Image Input (AREA)
  • Shift Register Type Memory (AREA)
  • Memory System (AREA)
JP9037683A 1997-02-21 1997-02-21 双方向転送型記憶装置及びメモリの入出力制御方法 Pending JPH10241354A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP9037683A JPH10241354A (ja) 1997-02-21 1997-02-21 双方向転送型記憶装置及びメモリの入出力制御方法
US08/876,048 US6067605A (en) 1997-02-21 1997-06-13 Bidirectional transfer type storage and method for controlling input and output of memory
KR1019970043250A KR100262434B1 (ko) 1997-02-21 1997-08-29 쌍방향 전송형 기억장치 및 메모리의 입출력 제어방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9037683A JPH10241354A (ja) 1997-02-21 1997-02-21 双方向転送型記憶装置及びメモリの入出力制御方法

Publications (2)

Publication Number Publication Date
JPH10241354A true JPH10241354A (ja) 1998-09-11
JPH10241354A5 JPH10241354A5 (cg-RX-API-DMAC7.html) 2004-09-09

Family

ID=12504406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9037683A Pending JPH10241354A (ja) 1997-02-21 1997-02-21 双方向転送型記憶装置及びメモリの入出力制御方法

Country Status (3)

Country Link
US (1) US6067605A (cg-RX-API-DMAC7.html)
JP (1) JPH10241354A (cg-RX-API-DMAC7.html)
KR (1) KR100262434B1 (cg-RX-API-DMAC7.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001013926A (ja) * 1999-06-25 2001-01-19 Sanyo Electric Co Ltd 表示装置の制御回路

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2417360B (en) * 2003-05-20 2007-03-28 Kagutech Ltd Digital backplane
US10690072B2 (en) 2016-10-19 2020-06-23 Ford Global Technologies, Llc Method and system for catalytic conversion

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5958689A (ja) * 1982-09-28 1984-04-04 Fujitsu Ltd 半導体記憶装置
US4665482A (en) * 1983-06-13 1987-05-12 Honeywell Information Systems Inc. Data multiplex control facility
JPH04248729A (ja) * 1991-02-05 1992-09-04 Fujitsu Ltd Ａｔｍ交換機
EP0778703A3 (en) * 1992-03-24 1999-03-31 Kabushiki Kaisha Toshiba Variable length code recording/playback apparatus
US5442282A (en) * 1992-07-02 1995-08-15 Lsi Logic Corporation Testing and exercising individual, unsingulated dies on a wafer
JPH06224933A (ja) * 1993-01-22 1994-08-12 Toshiba Corp バッファメモリ装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001013926A (ja) * 1999-06-25 2001-01-19 Sanyo Electric Co Ltd 表示装置の制御回路

Also Published As

Publication number Publication date
US6067605A (en) 2000-05-23
KR19980069917A (ko) 1998-10-26
KR100262434B1 (ko) 2000-08-01

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