JPH0964087A - セラミックケース - Google Patents

セラミックケース

Info

Publication number
JPH0964087A
JPH0964087A JP7221876A JP22187695A JPH0964087A JP H0964087 A JPH0964087 A JP H0964087A JP 7221876 A JP7221876 A JP 7221876A JP 22187695 A JP22187695 A JP 22187695A JP H0964087 A JPH0964087 A JP H0964087A
Authority
JP
Japan
Prior art keywords
stitches
layout
pellet
ceramic case
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7221876A
Other languages
English (en)
Other versions
JP2685037B2 (ja
Inventor
Kazutoshi Watanabe
和敏 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7221876A priority Critical patent/JP2685037B2/ja
Priority to US08/701,232 priority patent/US5801927A/en
Publication of JPH0964087A publication Critical patent/JPH0964087A/ja
Application granted granted Critical
Publication of JP2685037B2 publication Critical patent/JP2685037B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/06—Arrangements of circuit components or wiring on supporting structure on insulating boards, e.g. wiring harnesses
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/05599—Material
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    • H01L2224/061—Disposition
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    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/4917—Crossed wires
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
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    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/494—Connecting portions
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    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
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    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【課題】セラミックケースで、狭パッドピッチ千鳥レイ
アウトのペレットと通常のパッドレイアウトのペレット
のどちらも共用して搭載できることを目的とする。 【解決手段】セラミックケース１で、狭パッドピッチ千
鳥レイアウトのペレット３用のステッチ４の両外側に、
ステッチ４のＡ〜Ｃ，Ｋ〜Ｍと同電位のステッチ４の
Ａ′〜Ｃ′，Ｋ′〜Ｍ′を設けて、通常のパッドレイア
ウトのペレット２では両外側のステッチ４のＡ′〜
Ｃ′，Ｋ′〜Ｍ′を使用することでボンディングワイヤ
５の交差が発生しない。一方、狭パッドピッチ千鳥レイ
アウトのペレット３の場合は、ステッチ４のＡ〜Ｍを使
用することによりボンディングワイヤ５の交差の発生が
なく搭載できる。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明はセラミックケースに
関し、特に半導体装置に用いるセラミックケースに関す
る。
【０００２】
【従来の技術】従来のセラミックケースでは、図２の様
に、狭パッドピッチ千鳥レイアウトのペレット３を搭載
する場合、ボンディングワイヤ５の交差を防ぐためにボ
ンディングパッド６とセラミックケース１上のステッチ
４が平行になる様に配置されていた。また、一般的な通
常のパッドレイアウトのペレット２を搭載する場合は、
そのパッドレイアウトに対応した別々のセラミックケー
ス１を使用していた。
【０００３】
【発明が解決しようとする課題】この従来のセラミック
ケースでは、狭パッドピッチ千鳥レイアウトのペレット
３用のセラミックケース１に、通常のパッドレイアウト
のペレット２を搭載すると、図３に示す様に、ボンディ
ングワイヤの交差が発生し組み立てができなかった。こ
のため、狭パッドピッチ千鳥レイアウトのペレット３と
通常のパッドレイアウトのペレット２では別々のセラミ
ックケース１を使わなくてはならず、セラミックケース
１を共通にできないという問題点があった。
【０００４】本発明の目的は、通常のパッドレイアウト
のペレットと狭パッドピッチ千鳥レイアウトのペレット
を共用して搭載できるセラミックケースを提供すること
にある。
【０００５】
【課題を解決するための手段】本発明のセラミックケー
スは、狭パッドピッチ千鳥レイアウトのペレットのボン
ディングパッドに対応して配置された複数の千鳥レイア
ウトのステッチと、この複数の千鳥レイアウトのステッ
チの両外側の位置に、この複数の千鳥レイアウトのステ
ッチのうちの両外側に位置する所定の千鳥レイアウトの
ステッチと同電位で同数のステッチが配置されているこ
とを特徴とする。
【０００６】
【発明の実施の形態】次に本発明の実施の形態について
図面を参照して説明する。
【０００７】図１は本発明の実施の形態の一例を説明す
る平面図である。本発明の実施の形態の一例は、図１に
示す様に、セラミックケース１にはボンディングワイヤ
５にて通常のパッドレイアウトのペレット２上のボンデ
ィングパッド６と接続される複数のステッチ４が配置さ
れている。これらのステッチ４のうちのＡ〜Ｍは、狭パ
ッドピッチ千鳥レイアウトのペレット３のボンディング
パッド６と接続する様に配置されたものである。一方、
ステッチ４のうちのＡ′〜Ｃ′，Ｋ′〜Ｍ′はそれぞれ
複数のステッチ４のＡ〜Ｍの両外側に配置され、ステッ
チ４のＡ〜Ｃ，Ｋ〜Ｍとセラミックケース１の積層構造
の中で接続されており、同電位となっている。
【０００８】このセラミックケース１に狭パッドピッチ
千鳥レイアウトのペレット３を搭載する場合には、ステ
ッチ４のＡ〜Ｍを使用し、図２に示した様に接続する。
一方、通常のパッドレイアウトのペレット２を搭載する
場合には、ステッチ４のうちのＡ′〜Ｃ′，Ｄ〜Ｊ，
Ｋ′〜Ｍ′を使用する。このように、本実施の形態で
は、通常のパッドレイアウトのペレット２を搭載する場
合にはステッチ４のうちのＡ〜Ｃ，Ｋ〜Ｍを使用しない
ので、図３に示したボンディングワイヤ５の交差はなく
なり、１つのセラミックケース１で、通常のパッドレイ
アウトのペレット２と狭パッドピッチ千鳥レイアウトの
ペレット３の搭載が可能となる。
【０００９】ここで、通常のパッドレイアウトのペレッ
トのパッドとピッチが１５０〜２００μｍ，狭パッドピ
ッチ千鳥レイアウトのペレット３のパッドが６０〜１０
０μｍである場合に、本実施例では、セラミックケース
１のステッチ４のピッチは６０〜１００μｍとなる。
【００１０】
【発明の効果】以上説明した様に本発明は、半導体装置
用セラミックケースにおいて、狭パッドピッチ千鳥レイ
アウトのペレットのボンディングパッドに対応して配置
された複数の千鳥レイアウトのステッチと、この複数の
千鳥レイアウトのステッチの両外側の位置に、この複数
の千鳥レイアウトのステッチのうちの両外側に位置する
所定の千鳥レイアウトのステッチと同電位で同数のステ
ッチを配置することにより、従来、ボンディングワイヤ
が交差して短絡するために搭載できなかった通常のパッ
ドレイアウトのペレットを搭載することができる様にな
った。
【００１１】これにより、二種類のパッドレイアウトの
ペレットを共用して搭載できるセラミックケースを提供
できるという効果がある。
【図面の簡単な説明】
【図１】本発明の実施の形態の一例を説明する平面図で
ある。
【図２】従来の狭パッドピッチ千鳥レイアウトのペレッ
トのボンディングパッドとセラミックケース上のステッ
チとの接続を示す平面図である。
【図３】従来のセラミックケースに通常のパッドレイア
ウトのペレットを搭載した場合のボンディグワイヤの交
差を示す平面図である。
【符号の説明】
１ セラミックケース ２ 通常のパッドレイアウトのペレット ３ 狭パッドピッチ千鳥レイアウトのペレット ４ ステッチ ５ ボンディングワイヤ ６ ボンディングパッド

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】 狭パッドピッチ千鳥レイアウトのペレッ
    トのボンディングパッドに対応して配置された複数の千
    鳥レイアウトのステッチと、この複数の千鳥レイアウト
    のステッチの両外側の位置に、この複数の千鳥レイアウ
    トのステッチのうちの両外側に位置する所定の千鳥レイ
    アウトのステッチと同電位で同数のステッチが配置され
    ていることを特徴とするセラミックケース。
JP7221876A 1995-08-30 1995-08-30 セラミックケース Expired - Fee Related JP2685037B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP7221876A JP2685037B2 (ja) 1995-08-30 1995-08-30 セラミックケース
US08/701,232 US5801927A (en) 1995-08-30 1996-08-21 Ceramic package used for semiconductor chips different in layout of bonding pads

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7221876A JP2685037B2 (ja) 1995-08-30 1995-08-30 セラミックケース

Publications (2)

Publication Number Publication Date
JPH0964087A true JPH0964087A (ja) 1997-03-07
JP2685037B2 JP2685037B2 (ja) 1997-12-03

Family

ID=16773573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7221876A Expired - Fee Related JP2685037B2 (ja) 1995-08-30 1995-08-30 セラミックケース

Country Status (2)

Country Link
US (1) US5801927A (ja)
JP (1) JP2685037B2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7675168B2 (en) 2005-02-25 2010-03-09 Agere Systems Inc. Integrated circuit with staggered differential wire bond pairs

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5959845A (en) * 1997-09-18 1999-09-28 International Business Machines Corporation Universal chip carrier connector
US6008532A (en) * 1997-10-23 1999-12-28 Lsi Logic Corporation Integrated circuit package having bond fingers with alternate bonding areas
US6212077B1 (en) * 1999-01-25 2001-04-03 International Business Machines Corporation Built-in inspection template for a printed circuit
US6787926B2 (en) * 2001-09-05 2004-09-07 Taiwan Semiconductor Manufacturing Co., Ltd Wire stitch bond on an integrated circuit bond pad and method of making the same
US6940154B2 (en) * 2002-06-24 2005-09-06 Asat Limited Integrated circuit package and method of manufacturing the integrated circuit package
US20050285281A1 (en) * 2004-06-29 2005-12-29 Simmons Asher L Pad-limited integrated circuit
US20060001180A1 (en) * 2004-06-30 2006-01-05 Brian Taggart In-line wire bonding on a package, and method of assembling same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3716761A (en) * 1972-05-03 1973-02-13 Microsystems Int Ltd Universal interconnection structure for microelectronic devices
US4489365A (en) * 1982-09-17 1984-12-18 Burroughs Corporation Universal leadless chip carrier mounting pad

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7675168B2 (en) 2005-02-25 2010-03-09 Agere Systems Inc. Integrated circuit with staggered differential wire bond pairs
US8084857B2 (en) 2005-02-25 2011-12-27 Agere Systems Method and article of manufacture for wire bonding with staggered differential wire bond pairs

Also Published As

Publication number Publication date
JP2685037B2 (ja) 1997-12-03
US5801927A (en) 1998-09-01

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