JPH0636578Y2 - 半導体集積回路 - Google Patents

半導体集積回路

Info

Publication number
JPH0636578Y2
JPH0636578Y2 JP1987054367U JP5436787U JPH0636578Y2 JP H0636578 Y2 JPH0636578 Y2 JP H0636578Y2 JP 1987054367 U JP1987054367 U JP 1987054367U JP 5436787 U JP5436787 U JP 5436787U JP H0636578 Y2 JPH0636578 Y2 JP H0636578Y2
Authority
JP
Japan
Prior art keywords
pad
bonding
integrated circuit
chip
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1987054367U
Other languages
English (en)
Other versions
JPS63162534U (ja
Inventor
忠明 椎葉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1987054367U priority Critical patent/JPH0636578Y2/ja
Publication of JPS63162534U publication Critical patent/JPS63162534U/ja
Application granted granted Critical
Publication of JPH0636578Y2 publication Critical patent/JPH0636578Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605—Shape
    • H01L2224/06051—Bonding areas having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【考案の詳細な説明】 〔産業上の利用分野〕 本考案は半導体集積回路に関し、特に集積回路チップ上
のボンディングパッドに関する。
〔従来の技術〕
従来、この種の集積回路チップ（以下ICチップという）
のボンディングパッドの形状はワイヤボールの大きさに
基づいて定められた、ボンディング線１本当りに必要な
所定面積の正方形となっていた。
〔考案が解決しようとする問題点〕
上述した従来の半導体集積回路はICチップのボンディン
グパッドの形状はワイヤボールの大きさによって定めら
れた正方形となっているので、ひとたび位置を決めてレ
イアウトしてしまうと異なるリードフレームタイプの搭
載しようとした場合に既存のリードフレームでは組立歩
留上不都合な位置のパッドがあると新規に適切なリード
フレームを設計するか又はその不適切なパッド位置を変
更しなければならないという欠点があった。
このことは同一品種の半導体集積回路で数種類のリード
フレームを使いわけなければならない現状において極め
て不便であり、設計及び管理上の工数増加を余儀なくし
ている。
〔問題点を解決するための手段〕
本考案の半導体集積回路は、内部リードで支えられたア
イランドに搭載したICチップを有する半導体集積回路に
おいて、前記ICチップがボンディング線１本当りに必要
な所定面積を単位として、１単位面積の第１のボンディ
ングパッドと、前記第１のボンディングパッドを複数個
連結して直角に折れ曲ったかぎ形の平面形状を有し角に
配置された第２のボンディングパッドと、前記各パッド
に対応して設けられたパッドスルーホールを有するカバ
ー絶縁膜とを有し、前記第２のボンディングパッドのう
ち少なくとも１単位面積に該当する部分は前記カバー絶
縁膜で覆われているというものである。
〔実施例〕
次に、本考案の実施例について図面を参照して説明す
る。
第１図は本考案の第１の実施例の主要部を示すIC半製品
の平面図であり、リードフレームにICチップを搭載した
状態を示している。
この実施例は、内部リードで支えられたアイランド３に
搭載したICチップ１を有する半導体集積回路において、
ICチップ１がボンディング線１本当りに必要な所定面積
を単位として、１単位面積の第１のボンディングパッド
21と、第１のボンディングパッド21を３個連結して直角
に折れ曲ったかぎ形の平面形状を有し角に配置された第
２のボンディングパッド２−２と、前述の各パッドに対
応して設けられたパッドスルーホールを有するカバー絶
縁膜（図示せず）とを有し、第２のボンディングパッド
２−２のうち実際にボンディング線を接続していない２
単位面積に該当する部分はカバー絶縁膜で覆われている
というものである。
第２図は本考案の第２の実施例の主要部を示すIC半製品
の平面図である。
この実施例は、リードフレームの種類が第１の実施例と
異なっていて、第２のボンディングパッド２−２の実際
にボンディングされている部分が第１の実施例と異なっ
ている。
かぎ形の第２のボンディングパッド２−２は、第１の実
施例ではＹ方向にあるステッチにボンディング線で接続
されているが、第２の実施例ではアイランドを支えてい
る内部リードの位置が異なりICチップ角のかぎ形の第２
のボンディングパッドはＸ方向にあるステッチに接続さ
れている。勿論第１の実施例と同様にＹ方向にあるステ
ッチに接続することも一応可能であるが、ボンディング
線と内部リードが交差する危険が増大するので、図示の
ものに組立歩留上劣ることは明らかである。このように
第２のボンディングパッドをかぎ形にしICチップ（平面
形状は正方形又は長方形をしているのが普通である）の
角に配置しておくことにより、いくつかの種類のリード
フレームに同一のICチップ（パッドスルーホールの位置
はともかく）を搭載することが可能となる。
しかしながら第１図や第２図のボンディングパッドの形
状に合わせてパッドスルーホールを形成すると、耐湿性
の低下をまねくし、従来のボンディング機械の光学的パ
ターン認識による位置決め装置が使用できなくなる。
しかしながらこの問題は、個々のリードフレームの最適
なボンディング位置に基づいたパッドスルーホールを有
するカバーマスクを各々準備することによって解決され
る。なお以上の説明は第２のボンディングパッドが１個
しかない場合について記述したが、ICチップ上の１個に
制限するものではないのでICチップの四角のそれぞれに
各１個宛配置してもよい。
〔考案の効果〕
以上説明したように本考案は複数のボンディング線を接
続可能なかぎ形のボンディングパッドをICチップの少な
くとも一角に配置することにより、異なるタイプのリー
ドフレームに対しての各々最適な位置に従ってカバー絶
縁膜のパッドスルーホールの位置を変えることにより、
異なるタイプのリードフレームでの組立歩留低下をなく
したり、ICチップレイアウト変更や新規リードフレーム
設計の機会の回数を低減できる効果がある。
【図面の簡単な説明】
第１図および第２図はそれぞれ本考案の第１および第２
の実施例の主要部を示すIC半製品の平面図で、ICチップ
をリードフレームに搭載した状態を示す。 １……ICチップ、２−１……第１のボンディングパッ
ド、２−２……第２のボンディングパッド、３……アイ
ランド、４……内部リード、５……ステッチ、６……ボ
ンディング線、７……ワイヤボール。

Claims (1)

    【実用新案登録請求の範囲】
  1. 【請求項１】内部リードで支えられたアイランドに搭載
    したICチップを有する半導体集積回路において、前記IC
    チップがボンディング線１本当りに必要な所定面積を単
    位として、１単位面積の第１のボンディングパッドと、
    前記第１のボンディングパッドを複数個連結して直角に
    折れ曲ったかぎ形の平面形状を有し角に配置された第２
    のボンディングパッドと、前記各パッドに対応して設け
    られたパッドスルーホールを有するカバー絶縁膜とを有
    し、前記第２のボンディングパッドのうち少なくとも１
    単位面積に該当する部分は前記カバー絶縁膜で覆われて
    いることを特徴とする半導体集積回路。
JP1987054367U 1987-04-10 1987-04-10 半導体集積回路 Expired - Lifetime JPH0636578Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987054367U JPH0636578Y2 (ja) 1987-04-10 1987-04-10 半導体集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987054367U JPH0636578Y2 (ja) 1987-04-10 1987-04-10 半導体集積回路

Publications (2)

Publication Number Publication Date
JPS63162534U JPS63162534U (ja) 1988-10-24
JPH0636578Y2 true JPH0636578Y2 (ja) 1994-09-21

Family

ID=30881295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987054367U Expired - Lifetime JPH0636578Y2 (ja) 1987-04-10 1987-04-10 半導体集積回路

Country Status (1)

Country Link
JP (1) JPH0636578Y2 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8694722B2 (en) 2001-09-28 2014-04-08 Micron Technology, Inc. Memory systems
US9026721B2 (en) 1995-07-31 2015-05-05 Micron Technology, Inc. Managing defective areas of memory
US9213606B2 (en) 2002-02-22 2015-12-15 Micron Technology, Inc. Image rescue
US9576154B2 (en) 2004-04-30 2017-02-21 Micron Technology, Inc. Methods of operating storage systems including using a key to determine whether a password can be changed

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60101938A (ja) * 1983-11-07 1985-06-06 Nec Corp 半導体装置
JPS60113636U (ja) * 1984-01-06 1985-08-01 日本電気アイシーマイコンシステム株式会社 半導体集積回路装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9026721B2 (en) 1995-07-31 2015-05-05 Micron Technology, Inc. Managing defective areas of memory
US8694722B2 (en) 2001-09-28 2014-04-08 Micron Technology, Inc. Memory systems
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