JPH08139194A - 半導体デバイス上に電気接続を作製する方法および該方法により作製された電気接続を有する半導体デバイス - Google Patents

半導体デバイス上に電気接続を作製する方法および該方法により作製された電気接続を有する半導体デバイス

Info

Publication number
JPH08139194A
JPH08139194A JP7102527A JP10252795A JPH08139194A JP H08139194 A JPH08139194 A JP H08139194A JP 7102527 A JP7102527 A JP 7102527A JP 10252795 A JP10252795 A JP 10252795A JP H08139194 A JPH08139194 A JP H08139194A
Authority
JP
Japan
Prior art keywords
layer
organic
containing dielectric
dielectric layer
conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7102527A
Other languages
English (en)
Japanese (ja)
Inventor
Robert H Havemann
エイチ．ヘイブマン ロバート
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPH08139194A publication Critical patent/JPH08139194A/ja
Pending legal-status Critical Current

Links

Classifications

    • H10P14/40—
    • H10W20/076—
    • H10W20/077—
    • H10W20/082—
    • H10W20/48—
    • H10W20/495—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP7102527A 1994-04-28 1995-04-26 半導体デバイス上に電気接続を作製する方法および該方法により作製された電気接続を有する半導体デバイス Pending JPH08139194A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US23409994A 1994-04-28 1994-04-28
US234099 1994-04-28

Publications (1)

Publication Number Publication Date
JPH08139194A true JPH08139194A (ja) 1996-05-31

Family

ID=22879928

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7102527A Pending JPH08139194A (ja) 1994-04-28 1995-04-26 半導体デバイス上に電気接続を作製する方法および該方法により作製された電気接続を有する半導体デバイス

Country Status (6)

Country Link
US (1) US6188125B1 (cg-RX-API-DMAC10.html)
EP (1) EP0680085B1 (cg-RX-API-DMAC10.html)
JP (1) JPH08139194A (cg-RX-API-DMAC10.html)
KR (1) KR950034610A (cg-RX-API-DMAC10.html)
DE (1) DE69512125T2 (cg-RX-API-DMAC10.html)
TW (1) TW271005B (cg-RX-API-DMAC10.html)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6633082B1 (en) 1997-05-30 2003-10-14 Nec Corporation Semiconductor device and method for manufacturing the semiconductor device
US7015143B2 (en) 2002-06-04 2006-03-21 Oki Electric Industry Co., Ltd. Structure including multiple wire-layers and methods for forming the same
KR20210002324A (ko) * 2019-06-28 2021-01-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 백엔드 오브 라인 비아와 금속 라인간 마진 개선
US12255134B2 (en) 2019-06-28 2025-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of back end of line via to metal line margin improvement

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09129727A (ja) * 1995-10-30 1997-05-16 Nec Corp 半導体装置及びその製造方法
DE69737542T2 (de) * 1996-03-22 2007-12-13 Texas Instruments Inc., Dallas Halbleiterschaltung mit dielektrischer Schicht zwischen zwei Metallebenen und Verfahren zur Herstellung
FR2747511B1 (fr) * 1996-04-10 1998-09-04 Sgs Thomson Microelectronics Interconnexions multicouches a faible capacite parasite laterale
JPH10223624A (ja) 1997-02-06 1998-08-21 Nec Yamagata Ltd 半導体装置の製造方法
US6294455B1 (en) 1997-08-20 2001-09-25 Micron Technology, Inc. Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry
JP3199006B2 (ja) * 1997-11-18 2001-08-13 日本電気株式会社 層間絶縁膜の形成方法および絶縁膜形成装置
US6197696B1 (en) 1998-03-26 2001-03-06 Matsushita Electric Industrial Co., Ltd. Method for forming interconnection structure
FR2777697B1 (fr) 1998-04-16 2000-06-09 St Microelectronics Sa Circuit integre avec couche d'arret et procede de fabrication associe
US20010029091A1 (en) * 1998-04-17 2001-10-11 U.S. Philips Corporation Method for manufacturing an electronic device comprising an organic- containing material
JP3102409B2 (ja) * 1998-04-30 2000-10-23 日本電気株式会社 配線の形成方法及びプラズマアッシング装置
US6127263A (en) * 1998-07-10 2000-10-03 Applied Materials, Inc. Misalignment tolerant techniques for dual damascene fabrication
US6391771B1 (en) 1998-07-23 2002-05-21 Applied Materials, Inc. Integrated circuit interconnect lines having sidewall layers
TW437040B (en) 1998-08-12 2001-05-28 Applied Materials Inc Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics
US6071809A (en) * 1998-09-25 2000-06-06 Rockwell Semiconductor Systems, Inc. Methods for forming high-performing dual-damascene interconnect structures
US6225207B1 (en) 1998-10-01 2001-05-01 Applied Materials, Inc. Techniques for triple and quadruple damascene fabrication
US6309801B1 (en) 1998-11-18 2001-10-30 U.S. Philips Corporation Method of manufacturing an electronic device comprising two layers of organic-containing material
US6258732B1 (en) * 1999-02-04 2001-07-10 International Business Machines Corporation Method of forming a patterned organic dielectric layer on a substrate
US6770975B2 (en) * 1999-06-09 2004-08-03 Alliedsignal Inc. Integrated circuits with multiple low dielectric-constant inter-metal dielectrics
EP1077475A3 (en) 1999-08-11 2003-04-02 Applied Materials, Inc. Method of micromachining a multi-part cavity
DE19961103C2 (de) * 1999-12-17 2002-03-14 Infineon Technologies Ag Dielektrische Füllung von elektrischen Verdrahtungsebenen und Verfahren zur Herstellung einer elektrischen Verdrahtung
US6720249B1 (en) * 2000-04-17 2004-04-13 International Business Machines Corporation Protective hardmask for producing interconnect structures
DE10127934A1 (de) * 2001-06-08 2002-12-19 Infineon Technologies Ag Leiterbahnanordnung und Verfahren zum Herstellen einer gekapselten Leiterbahnkopplung
DE10146146B4 (de) * 2001-09-19 2004-02-05 Infineon Technologies Ag Verfahren zur elektrischen Isolation nebeneinander liegender metallischer Leiterbahnen und Halbleiterbauelement mit voneinander isolierten metallischen Leiterbahnen
US6878620B2 (en) * 2002-11-12 2005-04-12 Applied Materials, Inc. Side wall passivation films for damascene cu/low k electronic devices
DE10301243B4 (de) * 2003-01-15 2009-04-16 Infineon Technologies Ag Verfahren zum Herstellen einer integrierten Schaltungsanordnung, insbesondere mit Kondensatoranordnung
US7608538B2 (en) * 2007-01-05 2009-10-27 International Business Machines Corporation Formation of vertical devices by electroplating
US9505609B2 (en) * 2015-04-29 2016-11-29 Invensense, Inc. CMOS-MEMS integrated device with selective bond pad protection

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4523372A (en) * 1984-05-07 1985-06-18 Motorola, Inc. Process for fabricating semiconductor device
JPS6185844A (ja) * 1984-09-28 1986-05-01 シーメンス、アクチエンゲゼルヤフト 集積回路とその製法
JPH01235254A (ja) 1988-03-15 1989-09-20 Nec Corp 半導体装置及びその製造方法
JP2782801B2 (ja) * 1989-06-23 1998-08-06 日本電気株式会社 半導体装置の配線構造
JPH04174541A (ja) 1990-03-28 1992-06-22 Nec Corp 半導体集積回路及びその製造方法
JPH04233732A (ja) * 1990-08-16 1992-08-21 Motorola Inc 半導体の製造工程で使用するスピン・オン誘電体
US5284801A (en) * 1992-07-22 1994-02-08 Vlsi Technology, Inc. Methods of moisture protection in semiconductor devices utilizing polyimides for inter-metal dielectric
JPH0697299A (ja) * 1992-09-11 1994-04-08 Nec Yamagata Ltd 半導体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6633082B1 (en) 1997-05-30 2003-10-14 Nec Corporation Semiconductor device and method for manufacturing the semiconductor device
US7015143B2 (en) 2002-06-04 2006-03-21 Oki Electric Industry Co., Ltd. Structure including multiple wire-layers and methods for forming the same
KR20210002324A (ko) * 2019-06-28 2021-01-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 백엔드 오브 라인 비아와 금속 라인간 마진 개선
US11276638B2 (en) 2019-06-28 2022-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Back end of line via to metal line margin improvement
US12255134B2 (en) 2019-06-28 2025-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of back end of line via to metal line margin improvement

Also Published As

Publication number Publication date
US6188125B1 (en) 2001-02-13
EP0680085A1 (en) 1995-11-02
KR950034610A (ko) 1995-12-28
DE69512125D1 (de) 1999-10-21
DE69512125T2 (de) 2000-04-20
TW271005B (cg-RX-API-DMAC10.html) 1996-02-21
EP0680085B1 (en) 1999-09-15

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