JPH073668B2 - 入出力回路コンポーネントの位置決め方法及び入出力回路 - Google Patents

入出力回路コンポーネントの位置決め方法及び入出力回路

Info

Publication number
JPH073668B2
JPH073668B2 JP2337039A JP33703990A JPH073668B2 JP H073668 B2 JPH073668 B2 JP H073668B2 JP 2337039 A JP2337039 A JP 2337039A JP 33703990 A JP33703990 A JP 33703990A JP H073668 B2 JPH073668 B2 JP H073668B2
Authority
JP
Japan
Prior art keywords
input
components
circuit
sub
output circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2337039A
Other languages
English (en)
Japanese (ja)
Other versions
JPH03252871A (ja
Inventor
ロバート・ポール・マスレイド
パーソタム・トライカム・パテル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH03252871A publication Critical patent/JPH03252871A/ja
Publication of JPH073668B2 publication Critical patent/JPH073668B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/998—Input and output buffer/driver structures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2337039A 1990-01-29 1990-11-30 入出力回路コンポーネントの位置決め方法及び入出力回路 Expired - Lifetime JPH073668B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/471,892 US4988636A (en) 1990-01-29 1990-01-29 Method of making bit stack compatible input/output circuits
US471892 1990-01-29

Publications (2)

Publication Number Publication Date
JPH03252871A JPH03252871A (ja) 1991-11-12
JPH073668B2 true JPH073668B2 (ja) 1995-01-18

Family

ID=23873400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2337039A Expired - Lifetime JPH073668B2 (ja) 1990-01-29 1990-11-30 入出力回路コンポーネントの位置決め方法及び入出力回路

Country Status (9)

Country Link
US (1) US4988636A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0440332B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH073668B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR930006723B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CN (1) CN1020245C (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
AU (1) AU631709B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE69128434D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
MY (1) MY106061A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
SG (1) SG44408A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006086533A (ja) * 2004-09-14 2006-03-30 Agere Systems Inc 向上した一致性のためのガードリング

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0624903B1 (en) * 1993-04-28 1998-12-30 STMicroelectronics S.r.l. A modular integrated circuit structure
US5691218A (en) * 1993-07-01 1997-11-25 Lsi Logic Corporation Method of fabricating a programmable polysilicon gate array base cell structure
US5552333A (en) * 1994-09-16 1996-09-03 Lsi Logic Corporation Method for designing low profile variable width input/output cells
US5548747A (en) * 1995-02-10 1996-08-20 International Business Machines Corporation Bit stack wiring channel optimization with fixed macro placement and variable pin placement
US5760428A (en) * 1996-01-25 1998-06-02 Lsi Logic Corporation Variable width low profile gate array input/output architecture
US5698873A (en) * 1996-03-08 1997-12-16 Lsi Logic Corporation High density gate array base cell architecture
US6725439B1 (en) * 1998-01-29 2004-04-20 International Business Machines Corporation Method of automated design and checking for ESD robustness
US6086627A (en) * 1998-01-29 2000-07-11 International Business Machines Corporation Method of automated ESD protection level verification
US6073343A (en) * 1998-12-22 2000-06-13 General Electric Company Method of providing a variable guard ring width between detectors on a substrate
JP4629826B2 (ja) * 2000-02-22 2011-02-09 パナソニック株式会社 半導体集積回路装置
US6879023B1 (en) * 2000-03-22 2005-04-12 Broadcom Corporation Seal ring for integrated circuits
US6550047B1 (en) * 2000-10-02 2003-04-15 Artisan Components, Inc. Semiconductor chip input/output cell design and automated generation methods
FR2817657B1 (fr) * 2000-12-06 2003-09-26 St Microelectronics Sa Circuit integre a couplage par le substrat reduit
US7350160B2 (en) * 2003-06-24 2008-03-25 International Business Machines Corporation Method of displaying a guard ring within an integrated circuit
US7496877B2 (en) * 2005-08-11 2009-02-24 International Business Machines Corporation Electrostatic discharge failure avoidance through interaction between floorplanning and power routing

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3798606A (en) * 1971-12-17 1974-03-19 Ibm Bit partitioned monolithic circuit computer system
US3999214A (en) * 1974-06-26 1976-12-21 Ibm Corporation Wireable planar integrated circuit chip structure
US3968478A (en) * 1974-10-30 1976-07-06 Motorola, Inc. Chip topography for MOS interface circuit
US4006492A (en) * 1975-06-23 1977-02-01 International Business Machines Corporation High density semiconductor chip organization
EP0232796B1 (en) * 1980-11-24 1991-07-03 Texas Instruments Incorporated Pseudo-microprogramming in microprocessor with compressed control rom and with strip layout of busses, alu and registers
JPS57211248A (en) * 1981-06-22 1982-12-25 Hitachi Ltd Semiconductor integrated circuit device
JPS58137229A (ja) * 1982-02-09 1983-08-15 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
US4613940A (en) * 1982-11-09 1986-09-23 International Microelectronic Products Method and structure for use in designing and building electronic systems in integrated circuits
WO1985002062A1 (en) * 1983-10-31 1985-05-09 Storage Technology Partners Cmos integrated circuit configuration for eliminating latchup
JPH063826B2 (ja) * 1985-04-22 1994-01-12 日本電気株式会社 スタンダ−ドセルの周辺ブロツク配置方法
US4731643A (en) * 1985-10-21 1988-03-15 International Business Machines Corporation Logic-circuit layout for large-scale integrated circuits
US4746966A (en) * 1985-10-21 1988-05-24 International Business Machines Corporation Logic-circuit layout for large-scale integrated circuits
JPS63108733A (ja) * 1986-10-24 1988-05-13 Nec Corp 半導体集積回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006086533A (ja) * 2004-09-14 2006-03-30 Agere Systems Inc 向上した一致性のためのガードリング

Also Published As

Publication number Publication date
CN1053863A (zh) 1991-08-14
KR930006723B1 (ko) 1993-07-23
SG44408A1 (en) 1997-12-19
KR910015043A (ko) 1991-08-31
JPH03252871A (ja) 1991-11-12
US4988636A (en) 1991-01-29
CN1020245C (zh) 1993-04-07
EP0440332A3 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1994-01-19
AU6855790A (en) 1991-08-01
DE69128434D1 (de) 1998-01-29
MY106061A (en) 1995-03-31
AU631709B2 (en) 1992-12-03
EP0440332A2 (en) 1991-08-07
EP0440332B1 (en) 1997-12-17

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