DE69128434D1 - Bit-Stapel kompatible Eingangs/Ausgangsschaltung - Google Patents

Bit-Stapel kompatible Eingangs/Ausgangsschaltung

Info

Publication number
DE69128434D1
DE69128434D1 DE69128434T DE69128434T DE69128434D1 DE 69128434 D1 DE69128434 D1 DE 69128434D1 DE 69128434 T DE69128434 T DE 69128434T DE 69128434 T DE69128434 T DE 69128434T DE 69128434 D1 DE69128434 D1 DE 69128434D1
Authority
DE
Germany
Prior art keywords
output circuit
compatible input
bit stack
stack compatible
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69128434T
Other languages
English (en)
Inventor
Robert Paul Masleid
Parsotam Trikam Patel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69128434D1 publication Critical patent/DE69128434D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69128434T 1990-01-29 1991-01-04 Bit-Stapel kompatible Eingangs/Ausgangsschaltung Expired - Lifetime DE69128434D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/471,892 US4988636A (en) 1990-01-29 1990-01-29 Method of making bit stack compatible input/output circuits

Publications (1)

Publication Number Publication Date
DE69128434D1 true DE69128434D1 (de) 1998-01-29

Family

ID=23873400

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128434T Expired - Lifetime DE69128434D1 (de) 1990-01-29 1991-01-04 Bit-Stapel kompatible Eingangs/Ausgangsschaltung

Country Status (9)

Country Link
US (1) US4988636A (de)
EP (1) EP0440332B1 (de)
JP (1) JPH073668B2 (de)
KR (1) KR930006723B1 (de)
CN (1) CN1020245C (de)
AU (1) AU631709B2 (de)
DE (1) DE69128434D1 (de)
MY (1) MY106061A (de)
SG (1) SG44408A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69322855T2 (de) * 1993-04-28 1999-05-20 Stmicroelectronics S.R.L., Agrate Brianza, Mailand/Milano Modulare integrierte Schaltungsstruktur
US5691218A (en) * 1993-07-01 1997-11-25 Lsi Logic Corporation Method of fabricating a programmable polysilicon gate array base cell structure
US5552333A (en) * 1994-09-16 1996-09-03 Lsi Logic Corporation Method for designing low profile variable width input/output cells
US5548747A (en) * 1995-02-10 1996-08-20 International Business Machines Corporation Bit stack wiring channel optimization with fixed macro placement and variable pin placement
US5760428A (en) * 1996-01-25 1998-06-02 Lsi Logic Corporation Variable width low profile gate array input/output architecture
US5698873A (en) * 1996-03-08 1997-12-16 Lsi Logic Corporation High density gate array base cell architecture
US6086627A (en) * 1998-01-29 2000-07-11 International Business Machines Corporation Method of automated ESD protection level verification
US6725439B1 (en) * 1998-01-29 2004-04-20 International Business Machines Corporation Method of automated design and checking for ESD robustness
US6073343A (en) * 1998-12-22 2000-06-13 General Electric Company Method of providing a variable guard ring width between detectors on a substrate
JP4629826B2 (ja) * 2000-02-22 2011-02-09 パナソニック株式会社 半導体集積回路装置
US6879023B1 (en) * 2000-03-22 2005-04-12 Broadcom Corporation Seal ring for integrated circuits
US6550047B1 (en) * 2000-10-02 2003-04-15 Artisan Components, Inc. Semiconductor chip input/output cell design and automated generation methods
FR2817657B1 (fr) * 2000-12-06 2003-09-26 St Microelectronics Sa Circuit integre a couplage par le substrat reduit
US7350160B2 (en) * 2003-06-24 2008-03-25 International Business Machines Corporation Method of displaying a guard ring within an integrated circuit
US7253012B2 (en) * 2004-09-14 2007-08-07 Agere Systems, Inc. Guard ring for improved matching
US7496877B2 (en) * 2005-08-11 2009-02-24 International Business Machines Corporation Electrostatic discharge failure avoidance through interaction between floorplanning and power routing

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3798606A (en) * 1971-12-17 1974-03-19 Ibm Bit partitioned monolithic circuit computer system
US3999214A (en) * 1974-06-26 1976-12-21 Ibm Corporation Wireable planar integrated circuit chip structure
US3968478A (en) * 1974-10-30 1976-07-06 Motorola, Inc. Chip topography for MOS interface circuit
US4006492A (en) * 1975-06-23 1977-02-01 International Business Machines Corporation High density semiconductor chip organization
EP0052828B1 (de) * 1980-11-24 1989-04-19 Texas Instruments Incorporated Mikroprozessorsystem
JPS57211248A (en) * 1981-06-22 1982-12-25 Hitachi Ltd Semiconductor integrated circuit device
JPS58137229A (ja) * 1982-02-09 1983-08-15 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
US4613940A (en) * 1982-11-09 1986-09-23 International Microelectronic Products Method and structure for use in designing and building electronic systems in integrated circuits
WO1985002062A1 (en) * 1983-10-31 1985-05-09 Storage Technology Partners Cmos integrated circuit configuration for eliminating latchup
JPH063826B2 (ja) * 1985-04-22 1994-01-12 日本電気株式会社 スタンダ−ドセルの周辺ブロツク配置方法
US4731643A (en) * 1985-10-21 1988-03-15 International Business Machines Corporation Logic-circuit layout for large-scale integrated circuits
US4746966A (en) * 1985-10-21 1988-05-24 International Business Machines Corporation Logic-circuit layout for large-scale integrated circuits
JPS63108733A (ja) * 1986-10-24 1988-05-13 Nec Corp 半導体集積回路

Also Published As

Publication number Publication date
US4988636A (en) 1991-01-29
JPH03252871A (ja) 1991-11-12
CN1020245C (zh) 1993-04-07
JPH073668B2 (ja) 1995-01-18
MY106061A (en) 1995-03-31
EP0440332A2 (de) 1991-08-07
AU631709B2 (en) 1992-12-03
KR930006723B1 (ko) 1993-07-23
EP0440332A3 (de) 1994-01-19
SG44408A1 (en) 1997-12-19
KR910015043A (ko) 1991-08-31
EP0440332B1 (de) 1997-12-17
AU6855790A (en) 1991-08-01
CN1053863A (zh) 1991-08-14

Similar Documents

Publication Publication Date Title
DE68912277D1 (de) Ausgangspufferschaltung.
DE69412667D1 (de) Überspannungstolerante Ausgangspufferschaltung
DE69225508D1 (de) Ausgangsschaltung
DE69117553D1 (de) Ausgangsschaltung
DE3888220D1 (de) Datenausgabeschaltung.
DE3583537D1 (de) Cmos-eingabe-/ausgabeschaltung.
DE69123383D1 (de) MOS-Eingangsschaltung
DE69216773D1 (de) Ausgangspufferschaltung
DE69128434D1 (de) Bit-Stapel kompatible Eingangs/Ausgangsschaltung
DE3888703D1 (de) ECL-kompatible Eingangs-/Ausgangsschaltungen in CMOS-Technik.
DE3889612D1 (de) Dateneingangs-/-ausgangsschaltung.
DE69229315D1 (de) Ausgangs-Schaltkreis
NO901886L (no) Vekselretter-utgangskrets.
DE68910413D1 (de) Ausgangsschaltung.
DE68915351D1 (de) Ausgangschaltung.
DE69224572D1 (de) Geregelte BICMOS-Ausgangspufferschaltung
DE68923573D1 (de) Eingangsschaltungen.
DE68926807D1 (de) Erweiterte Eingabe-/Ausgabe-Schaltungsplatten-Adressierungsanordnung
DE69223676D1 (de) Ausgangspufferschaltung
DE69120097D1 (de) MOS-Ausgangsschaltung
DE69205522D1 (de) Eingangspufferschaltung.
DE69121125D1 (de) Informationsein-/ausgabevorrichtung
KR940021417U (ko) 출력 버퍼회로
KR930015983U (ko) 멀티 입출력 메모리장치
KR930007577U (ko) 출력회로

Legal Events

Date Code Title Description
8332 No legal effect for de