WO1985002062A1

WO1985002062A1 - Cmos integrated circuit configuration for eliminating latchup

Info

Publication number: WO1985002062A1
Application number: PCT/US1984/001708
Authority: WO
Inventors: John J. Zasio; Michael M. Chiang; James M. Lee
Original assignee: Storage Technology Partners
Priority date: 1983-10-31
Filing date: 1984-10-22
Publication date: 1985-05-09
Also published as: EP0160077A1

Abstract

An improved configuration for CMOS circuits which reduces the sensitivity to latchup. The configuration provides guard rings of P+ material (80, 81) and N+ material (82, 83) around the N channel and P channel transistors, respectively, of the input/output circuits (50, 51) of a CMOS chip. Elsewhere on the chip, a guard strip of P+ material (75-79) is placed adjacent to each contiguous group of N channel transistors, and a guard strip of N+ material (70-74) is placed adjacent to each contiguous group of P channel transistors. All of the P+ guard rings and guard strips are connected to the negative operating potential of the chip and all the N+ guard rings and guard strips are connected to the positive operating potential of the chip.

Description

CMOS INTEGRATED CIRCUIT CONFIGURATION FOR ELIMINATING LATCHUP

BACKGROUND OF THE INVENTION

This invention relates to complementary metal oxide semiconductor (CMOS) integrated circuits (ICs), and more particularly, to a configuration of- arranging the elements that make up the CMOS circuits on an IC chip so as to reduce, the latchup problem that is inherent in CMOS ICs of the prior art.

CMOS IC chips may be fabricated as small scale integration (SSI), chips, medium scale integration (MSI) chips, large scale integration (LSI) chips, or very large scale integration (VLSI) chips. The major difference between these four levels of integration is the number of transistors on the chip. Regardless of the level of integration used, CMOS chips include a multiplicity of complementary pairs of transistors. Each pair consists of an N channel transistor and a P channel transistor having a common gate. When one of the transistors is turned on, the other transistor of the pair is turned off. These complementary pairs are interconnected by metalization traces on the chip to form the desired circuits.

The sources and drains of the CMOS transistors are isolated from each other by reverse biased P-N junctions.

Disadvantageously, these P-N junctions also form undesirable NPN and PNP bipolar transistors. (The term "bipolar" is well understood in the art.) These bipolar transistors, the distributed resistances of the semiconductor material of the chip, and t e metal interconnections of the chip form a multiplicity of bipolar circuits within the semiconductor material of the chip. Under normal conditions, these bipolar circuits are inactive. However, under

_QMPI__ certain abnormal conditions, as explained below, these circuits may become active and turn on.

As explained more fully below, the bipolar circuits each consist of two transistors interconnected with positive feedback through the distributed resistance of the chip material. If one of the bipolar transistors begins to conduct, the feedback turns on the other bipolar transistor, which in turn causes the first to conduct more heavily, and so on. The bipolar circuit thus "latches up", drawing maximum current as limited by the distributed resistance, when one of the bipolar transistors in the pair begins to conduct. When in this condition, the CMOS elements that caused the bipolar transistors to be formed can not function.

Unfortunately, a mechanism exists, as will be explained in the description of the preferred embodiment, that allows the -latchup of one bipolar circuit on the chip to cause the other bipolar circuits on the chip to also latchup. Therefore, once a single bipolar circuit latches up, all the bipolar circuits within the chip will likely be in a state of latchup within a very short period of time, and the CMOS circuits of the chip become inoperative.

While latchup does not normally damage the CMOS circuits on the chip, even though it does make them inoperative while it is occurring, it may destroy the usefulness of the chip by reading the CMOS circuits inoperative or by preventing electrical connections from being made with the desired CMOS circuits. That is, when the bipolar circuits go into latchup, they draw current through the metal traces that make up the power distribution network of the chip. The positive and negative polarities of this power distribution network are each connected to a pin, or a number of pins, to a power source off of the chip. All the current entering the chip is therefore concentrated in a single trace, or a small number of traces. In the case of LSI and VLSI CMOS chips, the total current drawn during latchup may be enough to melt these traces, thereby destroying the usefulness of the chip. In the case of SSI and MSI CMOS chips, the total current drawn during latchup typically will not melt the traces. Thus, if the external power source is turned off, the latchup will cease and the SSI or MSI ODS chip will usually still function as designed when the power source is turned back on.

As additional background information, and in an effort to better define the latchup problem to which the present invention offers a solution, reference will now be made to FIGURES la-Id, wherein a typical CMOS circuit is shown in various forms. FIGURE la is a plan view of the elements of a simple CMOS circuit. Two N+ areas 13-14 are formed in a P- well 11, and two P+ areas- 17-18 are formed in an N- substrate 10. (Note, the terms "N", "P", ^MN+", "P-", "N-", or "P+" refer to the type or polarity of a semiconductor material and/or the relative doping thereof. These terms are well understood by those skilled in semiconductor art. A "P" typically connotes a positive doping polarity--the addition of holes--whereas an "N" connotes a negative doping polarity—the addition of elections.) A common polysilicon gate 12 is used to form a complementary pair of transistors: an N channel transistor 22 and a P channel transistor 23. The N channel transistor 22 consists of the drain (N+ 13), the source (N+ 14) and gate (polysilicon 12); while the P channel transistor 23 consists of the drain (P+ 18), the source (P+ 17), and the gate (polysilicon 12) .

A metallization trace 21 connects the source 17 of the P channel transistor 23 to the drain 13 of the N channel transistor 22. Additional metal traces 16 and 20 are used to connect the CMOS circuit to the positive (VDD) and negative (Ground) potentials

-SuR£l

OMPI necessary to operate the circuit. Metal trace 16 connects the source 14 of the N channel transistor 22 to a P+ area 15 which is connected to the ground distribution network of the chip (not shown in the figure), and metal trace 20 connects the drain of the P channel transistor 23 to an N+ area 19 which is connected to the VDD distribution network of the chip (not shown in the igure).

It is noted that the actual process steps used to form the elements that make up the simple circuit shown in FIGURE la are not material to the present invention. Moreover, such process steps are well understood by those knowledgeable in the art of CMOS technology. Accordingly, these process steps will not be discussed herein.

FIGURE lb is a schematic drawing of the simple CMOS circuit of FIGURE la. For consistency, the elements of the circuit are numbered the same even though they are represented in different forms in the two figures. The circuit is a CMOS inverter. When the signal IN is low, the P channel transistor 23 will be on, the N channel transistor 22 will be off, and the signal OUT will be high. When the signal IN is high, the two transistors 22-23 will be in the opposite states and the signal OUT will be low.

FIGURE lc is a cross sectional drawing that combines in one drawing the views of the cross sectional lines A-A and B-B of FIGURE la. Again, for consistency, like elements of FIGURES la and lc have the same numbers even though they are represented in a different form. In order for the CMOS circuit to function properly, the N- substrate 10 must be biased positive with respect to the P- well 11. This is done via the N+ material 19 and P+ material 15, respectively. A "+" material is more heavily doped than a "-" material, and therefore exhibits less resistance per unit length. For example, P+ and N+ materials have resistances of approximately 70 and 20 ohms/square, respectively; while P- and N- materials have resistances of approximately 4000 and 2000 ohms/square, respectively. (The unit "ohms/square" is also well understood by those knowledgeable in the art of semiconductor fabrication.) In addition, a metal trace makes better contact, i.e., lower contact resistance, with a "+" material than with a "-" material. Hence, the P+ region 15 is added to the P- well 11 and the N+ region 19 is added to the N- substrate 10 to provide a low contact resistance point, approximately 0.15 ohms per square, for the biasing potentials.

The resistors R1-R2 and R5-R6 are shown as dashed lines in FIGURE lc since they do not exist as physical resistors but represent the distributed resistance that is an inherent part of the N- substrate and P- well, respectively. They are shown as two resistors in each region only for illustrative purposes. Since it is a distributed resistance it could also be represented as a multiplicity of resistors.

As mentioned previously, when the various elements of a CMOS chip are interconnected to form a functional circuit, a bipolar circuit is also formed within the chip. FIGURE Id is a schematic drawing of such a bipolar circuit. It will be described in conjunction with FIGS, la-lc.

The resistors R1-R2 and R5-R6 are the same as those shown in FIGURE lc. The resistor R4 is the small contact resistance at the P+ material 18. The bipolar PNP transistor QI consists of the emitter, P+ material 18; the base, N+ substrate 10; and the collector, P- material 11. The open emitter 24 of QI is the P+ material 17 which, though connected in the CMOS circuit of FIGURE lb, also forms an open emitter in the bipolar circuit of FIGURE Id. The resistor R3 is the small contact resistance at the N+ material 14. The bipolar NPN transistor Q2 consists of the collector, N- substrate 10; the base, P- well 11; and the emitter, N+ material 14. The open emitter 25 of Q2 is the N+ material 13 which, though connected in the CMOS circuit of FIGURE lb, also forms an open emitter in the bipolar circuit of FIGURE Id.

It is thus seen that while the bipolar transistors QI and Q2 are formed as a result of the CMOS fabrication process, the biploar circuits are formed as a result of the placement of the metallization traces. That is, if there were no metal traces, R3 and R4 would not exist, and the bipolar circuit would not be connected to VDD and to ground.

Under normal conditions, the two transistors^" QI and Q2 of the bipolar circuit of FIGURE Id are off. The only current that flows in the chip is that of the CMOS circuits, between the N+ materials 13-14 or the P+ materials 17-18. Under these conditions the emitter of QI and the collector of Q2 will both be at a voltage potential of VDD volts through the resistors R4 and R1-R2, respectively. If transistor Q2 begins to conduct (the mechanisms that may cause QI or Q2 to begin to conduct are described below), a positive current will begin to flow from VDD, through R1-R2, Q2, and R3 to ground. If the voltage drop across RI exceeds one diode drop, i.e., approximately 0.7 Volts, transistor QI will begin to conduct since its base will be more than one diode drop more negative than its emitter. The current flow through QI will in turn cause a positive voltage drop across resistor R6. This positive potential, being applied to the base of Q2, causes Q2 to conduct even more current, thereby causing a larger voltage drop across R5, which causes QI to conduct more current, increasing the positive voltage drop across R6, and so forth. Within a few nanoseconds of having QI or Q2 begin to conduct, the two transistors Q1-Q2 are therefore latched up, and the CMOS circuits are inoperative.

As thus described, it is seen that the distributed resistances R1-R2 in the N- substrate and R5-R6 in the P- well provide a positive feedback mechanism in the bipolar circuit. If either of the transistors Q1-Q2 conducts enough to turn on the other transistor, this feedback causes the bipolar circuit to latchup.

A variety of mechanisms may cause one of the bipolar transistors to begin to conduct. For example, if the OUT signal of the CMOS circuit of FIGS, la-lc is connected to an output pin of the chip package, the open emitters 24-25 of the bipolar circuit are also connected to this output pin. If the open emitter 24 should go one diode drop higher than VDD, transistor QI will begin to conduct and if open emitter 25 should go one diode drop lower than ground potential, transistor Q2 will begin to conduct. Either of these conditions can be caused by such things as: the static discharge from an improperly grounded scope probe when it is applied to the output pin; improper sequencing of power supply turn on when multiple power supplies are used in a system; capacitive coupling of switching noise from adjacent signal wires, etc.

The ODS circuit does not have to be connected to an output pin in order for the bipolar transistors to start conducting. For example, capacitive coupling from other internal circuits can sometimes be sufficient to turn on one of the transistors. Also, mechanisms such as sufficiently intense visible light, ionizing radiation, e.g., X-rays, gamma rays, etc., can induce current flow in the open emitters 24 and 25 of FIGURE Id to start the latchup problem.

It is obvious from the above discussion that the use and application of CMOS technology is limited and affected by the problems caused by latchup. It is also obvious that any method that will reduce or eliminate the occurrence of latchup will enhance the art of CMOS technology. The present invention offers such a method.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a solution to the problem of latchup that occurs in CMOS circuits of the prior art. More particularly, the invention addresses the problem of latchup by eliminating or restricting the feedback mechanism that causes the latchup to occur. A primary object of the present invention is to reduce the feedback mechanism to a point where latchup will not occur in most applications of ODS integrated circuits.

The above and other objects of the. invention are realized through the.use of guard rings and guard strips that are selectively placed on the ODS chip as described below. The ODS chip is configured into two types of circuits: (1) a plurality of peripheral circuits around the periphery of the chip that serve as input/output (I/O) buffers, test circuits* and clock drivers; and (2) a multiplicity of circuits in the internal area of chip. Both of these types of circuits comprise contiguous groups of N channel transistors formed in the P- wells and contiguous groups of p channel transistors formed in the N- substrate. The actual number of transistors in each group varies with the type of circuit and the application of the chip. The transistors are selectively interconnected with metal traces to cause the chip to perform the desired function.

According to the present invention, a guard ring of P+ material is placed in the P- well around each contiguous group of N channel transistors in the I/O buffers. A similar guard ring of N+ material is placed in the N- substrate around each contiguous group of P channel transistors in the I/O buffers. Further, a guard strip of P+ material is placed in the P- well adjacent to each contiguous group of N channel transistors, and a guard strip of N+ material is placed in the N- substrate adjacent to each contiguous group of P channel transistors in the remaining circuits of the chip. The remaining circuits include the test circuits, clock drivers, and internal circuits.

The P+ guard rings and guard strips are all connected to the negative potential distribution network of the chip. These connections advantageously reduce the distributed resistance (RI of FIGURE Id) of the N- substrate between the positive potential and the P- well. Similarly, the N+ guard rings and guard strips are all connected to positive potential distribution network of the chip. , These multiple connections likewise reduce the distributed resistance (R6 of FIGURE Id) of the P- well between the negative potential and the N- substrate. Because latchup of the bipolar circuits formed within the CMOS chip is primarily caused by the positive feedback mechanism provided by the distributed resistances of the P- well and the N- substrate, the present invention thus meets its objectives by reducing these distributed resistances to the point where the feedback is not sufficient to allow latchup to occur.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more apparent from the following description of the preferred embodiment which is given in conjunction with the following drawings, wherein: FIGURE la is a plan view of the elements that make up a simple CMOS circuit;

FIGURE lb is a schematic drawing of the simple CMOS circuit of FIGURE la;

FIGURE lc is a cross sectional view of the semiconductor material of the circuit of FIGURE la, showing the physical relationship of the various elements that make up the simple CMOS circuit;

FIGURE Id is a schematic drawing of the bipolar circuit that is formed within the semiconductor material of a CMOS chip when the various CMOS elements are interconnected to form a ODS circuit;

FIGURE 2 is a representative layout of a CMOS chip showing the position of the various ODS circuits on a chip of the preferred embodiment of the present invention; .

FIGURE 3 is a plan view showing one possible arrangement of the transistors of the internal circuits of a CMOS chip;

FIGURE 4 is a cross sectional view of the transistors of FIGURE 3;

FIGURE 5 is a plan view showing one possible arrangement of the transistors of the peripheral circuits of a CMOS chip;

FIGURE 6 is a plan view, similar to FIGURE 3, showing the arrangement of the transistors of the internal circuits and includes the placement of guard strips in accordance with the present invention; and

FIGURE 7 is a plan view, similar to FIGURE 5, showing the preferred arrangement of the transistors of the peripheral circuits, and includes the placement of guard rings and strips in accordance with the present invention.

OMPI DETAILED DESCRIPTION OF THE INVENTION

The following is a description of the best presently contemplated mode of carrying out the present invention. This description is given only to illustrate the general principles of the invention and is not to be taken in a limiting sense. To ascertain the true scope of the invention, refer to the appended claims.

FIGURES la-d have been discussed previously . in the BACKGROUND section of this application.

FIGURE 2 is a representative layout showing the position of the CMOS circuits on a chip of the preferred embodiment. A plurality of circuits 31, called the peripheral circuits, are arranged around the periphery of the chip 30. The peripheral circuits 31 may include tri-state bi-directional input/output (I/O) circuits, test circuits, and clock driver circuits. The I/O circuits are connected to the pins of the packaged chip (not shown in the figure) and receive signals from off the chip and/or drive circuits off of the chip. A multiplicity of internal circuits 32, are arranged in an array within the peripheral circuits 31. These internal circuits 32 are selectively interconnected to each other and to the peripheral circuits by metal traces so as to cause the chip to perform the desired function.

FIGURE 3 is a plan view showing a typical arrangement of the transistors of the internal circuits 32 (FIGURE 2). A plurality of cells 35-42 are arranged in a column. Each cell includes two pairs of complementary transistors, with the N channel transistors being formed in the P- well 45 and the P channel transistors being formed in the N- substrate 46. A cell is analogous to the configuration shown in FIGURE la except two polysilicon gates 49-50 are used to form two pairs of complementary transistors per cell. Also shown in the figure are the P+ regions 43-44 in the P- well and the N+ regions 47-48 in the N- substrate 46. The P+ region 43-44 and the N+ regions 47-48 are connected to the negative and positive potential distribution networks, respectively, of -the chip (not shown in the figure).

FIGURE 4 is a cross sectional drawing that combines the three cross sectional lines C-C, D-D and E-E of FIGURE 3. It is shown to illustrate that in the configuration of FIGURE 3, the values of R1-R2 and R5-R6 can be quite large, depending upon where the transistor pair (or cell) in question is located in the column of cells. The further the cell is from the P+ and N+ regions 43 and 47, respectively, the larger the distributed resistance R1-R2 and R5-R6. Since a voltage drop of approximately 0.7 volts across RI or R6 is all that is required to cau§e latchup, as explained previously, and because this voltage drop is equal to IxR (where I is the current flowing through R), the larger the values of RI and R6, the smaller the current that will cause latchup. In order to minimize the likelihood of latchup, therefore, it is desirable to make RI and R6 as small as possible.

FIGURE 5 is a plan view of two types of peripheral circuits that may be used on a CMOS integrated circuit. The polysilicon gates are omitted for clarity. A first peripheral circuit, a tri-state bi-directional I/O circuit, is formed from N channel transistors 50 and P channel transistors 51. A second peripheral circuit, a clock driver circuit, is formed from N channel transistors 53-54 and P channel transistors 55-56. This clock driver circuit receives a clock signal from an external source via the I/O circuit (comprising transistors 50 •§ 51) and supplies the clock to all the circuits of the CMOS chip that require a clock signal. A shift register circuit may also be made from the N channel transistors 57 and P channel transistors 58. In a preferred ODS embodiment, every I/O pin of the chip, other than the clock inputs, has a shift register stage associated therewith in addition to the tri-state bi-directional I/O circuit. This shift register stage is used for testing purposes and is fully described in United States Patent Application Serial Number 332,866, filed 12-21-81, which is assigned to the same assignee as is this application.

Also shown in FIGURE 5 are P+ regions 60-61 in the P- well 59, and N+ regions 62-63 in N- substrate 46. The P+ regions 60-61 and N+ regions 62-63 are connected to the negative and positive potential distribution networks, respectively, of the chip (not shown in the figure). It is noted that FIGURE 5 is not drawn to any scale. However, the shapes 50-56 that make up the transistors are relatively large since the I/O drivers require more current than the internal circuits. Thus, the "feedback" resistors of the bipolar circuits formed will be physically relatively large, and their resistance values will also be relatively large.

The preferred embodiment of the present invention, shown in FIGURES 6 and 7, adds guard strips and rings to the circuits shown in FIGURES 3 and 5. Referring first to FIGURE 6, a plan view of the preferred arrangement of the transistors of the internal circuits 32 (FIGURE 2) is shown. The same cells 35-42 as shown in FIGURE 3 are shown in FIGURE 6. (The polysilicon gates are omitted in FIGURE 6 since they add nothing to this discussion.) However, in FIGURE 6, a P+ guard strip 75-79 is added in the P- well 45 between every other cell and an N+ guard strip 70-74 is added in the N- substrate between every other cell. Each of the P+ regions 75-79 and each of the N+ regions 70-74 are connected to the negative potential and positive potential distribution network, respectively, of the chip. Advantageously, the added P+ guard strips 75-79 cause every pair of N channel transistors to be adjacent to a P+ region, while the added N+ guard strips 70-74 causes every pair of P channel transistors to be adjacent to an N+ region. The result of this configuration is that the distributed resistances in the P- well and N- substrate of the internal circuits are kept very small. In turn, these small distributed resistances prevent the bipolar circuits (formed when the internal circuits are interconnected) from latching up.

FIGURE 7 is a plan view showing a preferred arrangement of the transistors of the peripheral circuits 31 (FIGURE 2). FIGURE 7 shows the same basic arrangement as is shown in FIGURE 5, but with some significant changes. The small N+ and P+ regions shown in FIGURE 5 have been replaced in FIGURE 7 by the N+ regions 82-85 and the P+ regions 80-81, respectively. These regions or guard rings 80-85 are all connected to the appropriate voltage potential with many contacts to metal to make a low resistance connection.

As can be seen in FIGURE 7, the transistors of the 1/0 circuits 50-51 are totally enclosed within a guard ring of the proper material. The transistors of the clock driver circuitry 53-56 and the transistors of the shift register 57-58, while not enclosed in guard rings, have guard strips of the appropriate material placed adjacent to them. The effect of the guard rings and guard strips is to reduce the distributed resistance of the P- well 59 and N- substrate 46. Advantageously, the resistance is reduced to the point that the bipolar circuits associated with the peripheral circuits will not latchup.

The guard rings and strips shown in FIGURES 6 § 7 are fabricated along with the other elements of the CMOS chip according to well known ODS circuitry fabrication techniques. It is to be emphasized

OMPI that the guard rings or strips are regions of appropriate N+ or P+ material that are electrically connected through metalization traces to an appropriate voltage potential (P+ to negative potential and N+ to positive potential) .

It is also noted that while the description herein has been relative to a preferred CMOS circuit using an N- substrate into which a P- well has been placed, the invention also contemplates a circuit having a P- substrate into which an N- well is placed.

Latchup tests performed on the circuit configurations of FIGURES 3-5 indicated that the entire chip went into latchup when approximately 15 ma of current was injected into an output pin of the chip. The addition of the guard rings around the transistors of the I/O circuit increased the current required to cause latchup to approximately 50 ma. Further, when latchup did occur, it did not occur in the I/O circuits, but occurred instead in the yet-to-be-protected internal circuits, and this latchup was caused by the mechanism previously mentioned in the BACKGROUND section of this application.

Further testing of the chip having a guard ring around the I/O circuits indicated that minority carriers injected into the substrate raised the P+ region more than 0.7 volts above the positive voltage potential VDD. These minority carriers were apparently not all attracted by the N+ guard ring 82. Rather, they have been found to travel more than 500 microns into the N- substrate, coming up in the internal P- wells. This causes a voltage rise on the P- wells, which in turn causes the NPN transistors to conduct, causing the bipolar circuit to latchup. This generates additional minority carriers, called stray currents, which can cause other internal circuits to latchup. Thus, if one internal circuit latches up, all may latchup. In contrast, through use of the

BUR ξ^*; Otøpi VATIO present invention, the distributed resistances in the P- well and the N- substrate, may be reduced, minimizing the effect of the stray currents in causing additional biploar circuits to latchup.

When all the guard rings, guard strips, and metal contacts of the invention, as shown in FIGURES 6 and 7 are added to a ODS chip, test results have indicated that latchup could not be induced by injecting up to 750 ma of current into the chip. Larger amounts of current could not be tried since the metal trace on the chip that was carrying the injected current melted. Thus, tests performed to date indicate that the invention advantageously reduces the sensitivity of CMOS circuits to latchup by at least a factor of 50. Further, since implementing the invention in ODS circuits that are used to realize a complex data processing system (a high-speed, high performance computer), no instances of latchup have been noted, whereas prior to implementing the invention, latchup was a recurring problem.

Claims

CLAIMSWhat is claimed is:

1. A method for reducing the possibility of latchup of a ODS integrated circuit (IC), said CMOS IC comprising regions of N- and P- material over which regions of P+ and N+ material are selectively placed in order to form P channel and N channel transistors, which transistors are in turn selectively interconnected to form desired functional CMOS circuits, said method comprising the steps of:

(a) selectively forming a guard channel around or near groups of said transistors, said guard channel comprising a P+ channel if placed in the P- material, and an N+ channel if placed in the N- material; and ■

(b) connecting all of said guard channels to an appropriate voltage potential, the P+ guard channels being connected to a negative potential, and the N+ guard channels being connected to a positive potential.

2. The method of claim 1 wherein the functional ODS circuits of said CMOS IC include input/output (I/O) circuits and non-I/0 circuits, and wherein step (a) comprises:

(1) encircling the transistors of said I/O circuits with rings of said guard channels, and

(2) placing strips of said guard channels near selected groups of the transistors of said non-I/0 circuits.

3. In a CMOS integrated circuit (IC) comprising N- and P- regions, each region having a distributed resistance associated therewith, and wherein regions of P+ and N+ material are selectively formed and positioned over said N- and P- regions so as to create P channel and N channel transistors, which P channel and N channel transistors are selectively interconnected to form desired functional ODS circuits, and which ODS circuits include input/output (I/O) circuits and non-I/0 circuits; and wherein bipolar circuits, comprising bipolar transistors formed by a particular combination of the P-, N-, P+, or N+ regions, and the distributed resistances of these same regions, may turn on and latchup if stray currents of sufficient magnitude are introduced into said N- or P- regions, which latchup condition of said bipolar circuits disadvantageously renders said functional ODS circuits of said IC inoperative, a method for reducing the distributed resistance of said N- or P- regions, thereby increasing the amount of stray current required to latchup said bipolar circuits, said method comprising the steps of:

(a) forming a ring of P+ material in the P- region around the N channel transistors of each I/O circuit;

(b) forming a ring of N+ material in the N- region around the P channel transistors of each I/O circuit;

(c) connecting said P+ rings to a negative voltage potential; and

(d) connecting said N+ rings to a positive voltage potential.

4. The method of claim 3 further comprising the steps of:

(e) forming a strip of P+ material in the P- region adjacent to selected groups of contiguous N channel transistors of the non-I/0 circuits; (f) forming a strip of N+ material in the N- region adjacent to selected groups of contiguous P channel transistors of the non-I/0 circuits; and

(g) connecting said P+ strips and N+ strips to said negative and positive voltage potentials, respectively.

5. The method of claim 4 wherein said P- region of said IC is a P- well embedded in an N- substrate, said N- region of said IC comprising said N- substrate.

6. An integrated circuit (IC) comprising: a substrate having a first doping polarity; at least one well having a second doping polarity embedded into said substrate; means for forming transistors out of selected portions of said substrate and well, each transistor including a channel having one of said first or second doping polarities through which current may flow between first and second electrical contact areas as controlled by a control signal applied to a third electrical contact area; means for selectively interconnecting the contact area of said transistors so as to form a plurality of desired functional circuits when said IC is coupled to a positive and a negative voltage potential, said electrical circuits including input/output (I/O) circuits and non-I/0 circuits; guard rings placed around the transistors of selected I/O circuits, each of said guard rings comprising a channel having a doping polarity the same as the substrate or well where said guard ring is located, but said guard ring having a higher doping concentration than that of its corresponding substrate or well; and means for electrically connecting each of said guard rings to an appropriate voltage potential so that stray currents flowing in said substrate or well may be captured by said guard ring and returned to said voltage potential.

7. The IC of claim 6 further comprising: guard strips placed near selected groups of transistors of said non-I/0 circuits each of said guard strips having a doping polarity the same as the substrate or well where said guard strip is located, but said guard strip having a higher doping concentration than that of its corresponding substrate or well; means for electrically connecting each of said guard strips to an appropriate voltage potential so that stray currents flowing in said substrate or well may be captured by said guard strips and returned to said voltage potential.

8. The IC of claim 7 wherein said IC is a complementary metal oxide semiconductor (CMOS) IC

9. The IC of claim 8 wherein the first doping polarity and concentration of said substrate is N-, and the second doping polarity and concentration of said well is P-, and wherein N channel transistors are formed in the P- well and P channel transistors are formed in the N-substrate; and further wherein the guard rings and strips have a doping polarity and concentration of P+, if located in the P- well, and N+, if located in the N- substrate.

10. The IC of claim 9 wherein said guard rings are placed around each transistor of each I/O circuit, a P+ ring being placed in the P- well around each N channel transistor, and an N+^* ring

being placed in the N- substrate around each P channel transistor, said P+ and N+ rings being electrically connected to the negative and positive voltage potentials, respectively.

11. The IC of claim 9 wherein said guard strips are placed adjacent to contiguous groups of transistors of the same channel polarity, a P+ strip being placed in the P- well adjacent to contiguous groups of N channel transistors, and an N+ strip being placed in the N- substrate adjacent to contiguous groups of P channel transistors, said P+ and N+ strips being electrically connected to the negative and positive voltage potentials, respectively.