KR930015983U - 멀티 입출력 메모리장치 - Google Patents

멀티 입출력 메모리장치

Info

Publication number
KR930015983U
KR930015983U KR2019910023852U KR910023852U KR930015983U KR 930015983 U KR930015983 U KR 930015983U KR 2019910023852 U KR2019910023852 U KR 2019910023852U KR 910023852 U KR910023852 U KR 910023852U KR 930015983 U KR930015983 U KR 930015983U
Authority
KR
South Korea
Prior art keywords
memory device
output memory
multi input
input
output
Prior art date
Application number
KR2019910023852U
Other languages
English (en)
Other versions
KR0123061Y1 (ko
Inventor
민병무
Original Assignee
엘지반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지반도체주식회사 filed Critical 엘지반도체주식회사
Priority to KR2019910023852U priority Critical patent/KR0123061Y1/ko
Publication of KR930015983U publication Critical patent/KR930015983U/ko
Application granted granted Critical
Publication of KR0123061Y1 publication Critical patent/KR0123061Y1/ko

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
KR2019910023852U 1991-12-24 1991-12-24 멀티 입출력 메모리장치 KR0123061Y1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019910023852U KR0123061Y1 (ko) 1991-12-24 1991-12-24 멀티 입출력 메모리장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019910023852U KR0123061Y1 (ko) 1991-12-24 1991-12-24 멀티 입출력 메모리장치

Publications (2)

Publication Number Publication Date
KR930015983U true KR930015983U (ko) 1993-07-28
KR0123061Y1 KR0123061Y1 (ko) 1999-02-18

Family

ID=19325523

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019910023852U KR0123061Y1 (ko) 1991-12-24 1991-12-24 멀티 입출력 메모리장치

Country Status (1)

Country Link
KR (1) KR0123061Y1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100465875B1 (ko) * 2002-06-07 2005-01-13 삼성전자주식회사 내장 메모리 소자들의 패드 연결구조

Also Published As

Publication number Publication date
KR0123061Y1 (ko) 1999-02-18

Similar Documents

Publication Publication Date Title
DE69132227T2 (de) Eingang-/Ausgangsteuerungseinrichtung
DE69221927T2 (de) Zeicheneingabegerät
DE69225508D1 (de) Ausgangsschaltung
DE69306349T2 (de) Ausgabegerät
DE69216773D1 (de) Ausgangspufferschaltung
DE69229315T2 (de) Ausgangs-Schaltkreis
DE69129431T2 (de) Ausgangsvorrichtung
DE69215314T2 (de) Eingabeeinheit
DE69223676T2 (de) Ausgangspufferschaltung
DE69109455T2 (de) Ausgangsvorrichtung.
DE69201261D1 (de) Ausgabeeinrichtung.
DE69121125T2 (de) Informationsein-/ausgabevorrichtung
DE69223183D1 (de) Nichtflüchtige Speicheranordnung
DE69218270T2 (de) Ausgangskontroll-Schaltkreis
DE69129128D1 (de) Ausgabegerät
KR930015983U (ko) 멀티 입출력 메모리장치
KR920022313U (ko) 멀티 플렉서의 출력 제어장치
DE69324943T2 (de) Ausgabegerät
KR930007750U (ko) 영상 메모리 입.출력 장치
KR950020598U (ko) 메모리 데이타 입출력 장치
DE69206122D1 (de) Ausgabevorrichtung.
KR930007201U (ko) 배지 트레이 장치
KR950009667U (ko) 데이타의 입출력장치
IT9021455A0 (it) Dispositivo di memoria a due ingressi
KR930003783U (ko) 입력버퍼회로

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 20050422

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee