KR930006723B1 - 다수의 입/출력회로소자 배치방법 및 집적회로의 입/출력회로 - Google Patents

다수의 입/출력회로소자 배치방법 및 집적회로의 입/출력회로 Download PDF

Info

Publication number
KR930006723B1
KR930006723B1 KR1019900022552A KR900022552A KR930006723B1 KR 930006723 B1 KR930006723 B1 KR 930006723B1 KR 1019900022552 A KR1019900022552 A KR 1019900022552A KR 900022552 A KR900022552 A KR 900022552A KR 930006723 B1 KR930006723 B1 KR 930006723B1
Authority
KR
South Korea
Prior art keywords
input
circuit
output
output circuit
elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019900022552A
Other languages
English (en)
Korean (ko)
Other versions
KR910015043A (ko
Inventor
폴 매스레이드 로버트
트리캄 파텔 파소탐
Original Assignee
인터내셔널 비지네스 머신즈 코포레이션
하워드 지, 피거로아
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 인터내셔널 비지네스 머신즈 코포레이션, 하워드 지, 피거로아 filed Critical 인터내셔널 비지네스 머신즈 코포레이션
Publication of KR910015043A publication Critical patent/KR910015043A/ko
Application granted granted Critical
Publication of KR930006723B1 publication Critical patent/KR930006723B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/998—Input and output buffer/driver structures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1019900022552A 1990-01-29 1990-12-27 다수의 입/출력회로소자 배치방법 및 집적회로의 입/출력회로 Expired - Fee Related KR930006723B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US471,892 1990-01-29
US07/471,892 US4988636A (en) 1990-01-29 1990-01-29 Method of making bit stack compatible input/output circuits

Publications (2)

Publication Number Publication Date
KR910015043A KR910015043A (ko) 1991-08-31
KR930006723B1 true KR930006723B1 (ko) 1993-07-23

Family

ID=23873400

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900022552A Expired - Fee Related KR930006723B1 (ko) 1990-01-29 1990-12-27 다수의 입/출력회로소자 배치방법 및 집적회로의 입/출력회로

Country Status (9)

Country Link
US (1) US4988636A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0440332B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH073668B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR930006723B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CN (1) CN1020245C (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
AU (1) AU631709B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE69128434D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
MY (1) MY106061A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
SG (1) SG44408A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69322855T2 (de) * 1993-04-28 1999-05-20 Stmicroelectronics S.R.L., Agrate Brianza, Mailand/Milano Modulare integrierte Schaltungsstruktur
US5691218A (en) * 1993-07-01 1997-11-25 Lsi Logic Corporation Method of fabricating a programmable polysilicon gate array base cell structure
US5552333A (en) * 1994-09-16 1996-09-03 Lsi Logic Corporation Method for designing low profile variable width input/output cells
US5548747A (en) * 1995-02-10 1996-08-20 International Business Machines Corporation Bit stack wiring channel optimization with fixed macro placement and variable pin placement
US5760428A (en) * 1996-01-25 1998-06-02 Lsi Logic Corporation Variable width low profile gate array input/output architecture
US5698873A (en) * 1996-03-08 1997-12-16 Lsi Logic Corporation High density gate array base cell architecture
US6725439B1 (en) * 1998-01-29 2004-04-20 International Business Machines Corporation Method of automated design and checking for ESD robustness
US6086627A (en) * 1998-01-29 2000-07-11 International Business Machines Corporation Method of automated ESD protection level verification
US6073343A (en) * 1998-12-22 2000-06-13 General Electric Company Method of providing a variable guard ring width between detectors on a substrate
JP4629826B2 (ja) * 2000-02-22 2011-02-09 パナソニック株式会社 半導体集積回路装置
US6879023B1 (en) * 2000-03-22 2005-04-12 Broadcom Corporation Seal ring for integrated circuits
US6550047B1 (en) * 2000-10-02 2003-04-15 Artisan Components, Inc. Semiconductor chip input/output cell design and automated generation methods
FR2817657B1 (fr) * 2000-12-06 2003-09-26 St Microelectronics Sa Circuit integre a couplage par le substrat reduit
US7350160B2 (en) * 2003-06-24 2008-03-25 International Business Machines Corporation Method of displaying a guard ring within an integrated circuit
US7253012B2 (en) * 2004-09-14 2007-08-07 Agere Systems, Inc. Guard ring for improved matching
US7496877B2 (en) * 2005-08-11 2009-02-24 International Business Machines Corporation Electrostatic discharge failure avoidance through interaction between floorplanning and power routing

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3798606A (en) * 1971-12-17 1974-03-19 Ibm Bit partitioned monolithic circuit computer system
US3999214A (en) * 1974-06-26 1976-12-21 Ibm Corporation Wireable planar integrated circuit chip structure
US3968478A (en) * 1974-10-30 1976-07-06 Motorola, Inc. Chip topography for MOS interface circuit
US4006492A (en) * 1975-06-23 1977-02-01 International Business Machines Corporation High density semiconductor chip organization
DE3177249D1 (de) * 1980-11-24 1991-08-08 Texas Instruments Inc Pseudo-mikroprogrammsteuerung in einem mikroprozessor mit komprimiertem steuerfestwertspeicher und mit bandanordnung von sammelschienen, alu und registern.
JPS57211248A (en) * 1981-06-22 1982-12-25 Hitachi Ltd Semiconductor integrated circuit device
JPS58137229A (ja) * 1982-02-09 1983-08-15 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
US4613940A (en) * 1982-11-09 1986-09-23 International Microelectronic Products Method and structure for use in designing and building electronic systems in integrated circuits
WO1985002062A1 (en) * 1983-10-31 1985-05-09 Storage Technology Partners Cmos integrated circuit configuration for eliminating latchup
JPH063826B2 (ja) * 1985-04-22 1994-01-12 日本電気株式会社 スタンダ−ドセルの周辺ブロツク配置方法
US4731643A (en) * 1985-10-21 1988-03-15 International Business Machines Corporation Logic-circuit layout for large-scale integrated circuits
US4746966A (en) * 1985-10-21 1988-05-24 International Business Machines Corporation Logic-circuit layout for large-scale integrated circuits
JPS63108733A (ja) * 1986-10-24 1988-05-13 Nec Corp 半導体集積回路

Also Published As

Publication number Publication date
EP0440332A3 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1994-01-19
JPH073668B2 (ja) 1995-01-18
AU6855790A (en) 1991-08-01
JPH03252871A (ja) 1991-11-12
SG44408A1 (en) 1997-12-19
EP0440332B1 (en) 1997-12-17
AU631709B2 (en) 1992-12-03
CN1053863A (zh) 1991-08-14
KR910015043A (ko) 1991-08-31
US4988636A (en) 1991-01-29
EP0440332A2 (en) 1991-08-07
DE69128434D1 (de) 1998-01-29
CN1020245C (zh) 1993-04-07
MY106061A (en) 1995-03-31

Similar Documents

Publication Publication Date Title
KR930006723B1 (ko) 다수의 입/출력회로소자 배치방법 및 집적회로의 입/출력회로
US10692856B2 (en) Semiconductor integrated circuit device
US7329938B2 (en) Semiconductor integrated circuit
US6222213B1 (en) Semiconductor integrated circuit device
US20030178648A1 (en) Gate array core cell for VLSI ASIC devices
US5671397A (en) Sea-of-cells array of transistors
US4786613A (en) Method of combining gate array and standard cell circuits on a common semiconductor chip
TW201926628A (zh) 具靜電放電防護之元件
US5045913A (en) Bit stack compatible input/output circuits
US5369595A (en) Method of combining gate array and standard cell circuits on a common semiconductor chip
US5311048A (en) Semiconductor integrated circuit device
US7895559B2 (en) Method for designing structured ASICs in silicon processes with three unique masking steps
US7165232B2 (en) I/O circuit placement method and semiconductor device
US5291043A (en) Semiconductor integrated circuit device having gate array
US6657264B2 (en) Layout method of latch-up prevention circuit of a semiconductor device
US6028341A (en) Latch up protection and yield improvement device for IC array
KR20020042507A (ko) 반도체장치, 그 제조방법 및 기억매체
US20250192045A1 (en) Semiconductor integrated circuit device
US20250151412A1 (en) Semiconductor integrated circuit device
JPH0566737B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP5385575B2 (ja) 半導体記憶装置
JP2000012697A (ja) 半導体チップ構造およびその設計方法

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

G160 Decision to publish patent application
PG1605 Publication of application before grant of patent

St.27 status event code: A-2-2-Q10-Q13-nap-PG1605

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

L13-X000 Limitation or reissue of ip right requested

St.27 status event code: A-2-3-L10-L13-lim-X000

U15-X000 Partial renewal or maintenance fee paid modifying the ip right scope

St.27 status event code: A-4-4-U10-U15-oth-X000

FPAY Annual fee payment

Payment date: 20020628

Year of fee payment: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20030724

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20030724

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000