JPH06204842A - Ｅｃｌ差動信号を受取りｃｍｏｓ互換性のある出力信号を発生するための論理インターフェース回路 - Google Patents

Ｅｃｌ差動信号を受取りｃｍｏｓ互換性のある出力信号を発生するための論理インターフェース回路

Info

Publication number
JPH06204842A
JPH06204842A JP5173989A JP17398993A JPH06204842A JP H06204842 A JPH06204842 A JP H06204842A JP 5173989 A JP5173989 A JP 5173989A JP 17398993 A JP17398993 A JP 17398993A JP H06204842 A JPH06204842 A JP H06204842A
Authority
JP
Japan
Prior art keywords
output
interface circuit
cmos
input
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5173989A
Other languages
English (en)
Japanese (ja)
Inventor
Ann K Woo
アン・ケイ・ウー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JPH06204842A publication Critical patent/JPH06204842A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Pulse Circuits (AREA)
JP5173989A 1992-08-28 1993-07-14 Ｅｃｌ差動信号を受取りｃｍｏｓ互換性のある出力信号を発生するための論理インターフェース回路 Withdrawn JPH06204842A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US935886 1986-11-28
US07/935,886 US5264745A (en) 1992-08-28 1992-08-28 Recovering phase and data from distorted duty cycles caused by ECL-to-CMOS translator

Publications (1)

Publication Number Publication Date
JPH06204842A true JPH06204842A (ja) 1994-07-22

Family

ID=25467843

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5173989A Withdrawn JPH06204842A (ja) 1992-08-28 1993-07-14 Ｅｃｌ差動信号を受取りｃｍｏｓ互換性のある出力信号を発生するための論理インターフェース回路

Country Status (6)

Country Link
US (1) US5264745A (en, 2012)
EP (1) EP0584946B1 (en, 2012)
JP (1) JPH06204842A (en, 2012)
KR (1) KR940005015A (en, 2012)
DE (1) DE69316680T2 (en, 2012)
TW (1) TW231385B (en, 2012)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5391945A (en) * 1993-09-24 1995-02-21 Motorola, Inc. Circuit and method for providing phase synchronization of ECL and TTL/CMOS signals
US5450024A (en) * 1994-01-19 1995-09-12 Alcatel Network Systems, Inc. ECL to CMOS signal converter circuit including toggle-fault detection
KR19980023243A (ko) * 1996-09-25 1998-07-06 황선두 2,2,6,6-테트라메틸-4-피페리디놀 에스테르 유도체의 정제 방법
US5886539A (en) * 1997-04-10 1999-03-23 Advanced Micro Devices, Ind Communication within an integrated circuit by data serialization through a metal plane
GB9708865D0 (en) * 1997-04-30 1997-06-25 Phoenix Vlsi Consultants Ltd ECL-CMOS converter
US5903521A (en) * 1997-07-11 1999-05-11 Advanced Micro Devices, Inc. Floating point timer
US6122278A (en) * 1997-08-07 2000-09-19 Advanced Micro Devices, Inc. Circuit and method for protocol header decoding and packet routing
US5943206A (en) * 1997-08-19 1999-08-24 Advanced Micro Devices, Inc. Chip temperature protection using delay lines
US5890100A (en) * 1997-08-19 1999-03-30 Advanced Micro Devices, Inc. Chip temperature monitor using delay lines
US5952868A (en) * 1997-09-18 1999-09-14 Cypress Semiconductor Corp. Voltage level interface circuit with set-up and hold control
US6192069B1 (en) 1997-11-03 2001-02-20 Advanced Micro Devices, Inc. Circuit and methodology for transferring signals between semiconductor devices
US6084933A (en) * 1997-11-17 2000-07-04 Advanced Micro Devices, Inc. Chip operating conditions compensated clock generation
US6031473A (en) * 1997-11-17 2000-02-29 Advanced Micro Devices, Inc. Digital communications using serialized delay line
US5852616A (en) * 1997-11-17 1998-12-22 Advanced Micro Devices, Inc. On-chip operating condition recorder
US5942937A (en) * 1997-11-19 1999-08-24 Advanced Micro Devices, Inc. Signal detection circuit using a plurality of delay stages with edge detection logic
US6091348A (en) * 1997-12-18 2000-07-18 Advanced Micro Devices, Inc. Circuit and method for on-the-fly bit detection and substitution
US5900834A (en) * 1997-12-18 1999-05-04 Advanced Micro Devices, Inc. Doppler shift detector
US6078627A (en) * 1997-12-18 2000-06-20 Advanced Micro Devices, Inc. Circuit and method for multilevel signal decoding, descrambling, and error detection
US6178208B1 (en) 1997-12-18 2001-01-23 Legerity System for recovery of digital data from amplitude and phase modulated line signals using delay lines
US6255969B1 (en) * 1997-12-18 2001-07-03 Advanced Micro Devices, Inc. Circuit and method for high speed bit stream capture using a digital delay line
US6046620A (en) * 1997-12-18 2000-04-04 Advanced Micro Devices, Inc. Programmable delay line
US6064232A (en) * 1997-12-18 2000-05-16 Advanced Micro Devices, Inc. Self-clocked logic circuit and methodology
US6218880B1 (en) 1997-12-18 2001-04-17 Legerity Analog delay line implemented with a digital delay line technique
US6160856A (en) * 1997-12-18 2000-12-12 Advanced Micro Devices, Inc. System for providing amplitude and phase modulation of line signals using delay lines
US6222392B1 (en) 1998-04-17 2001-04-24 Advanced Micro Devices, Inc. Signal monitoring circuit for detecting asynchronous clock loss
US6339833B1 (en) 1998-04-17 2002-01-15 Advanced Micro Devices, Inc. Automatic recovery from clock signal loss
US6323701B1 (en) 1998-12-28 2001-11-27 Cypress Semiconductor Corporation Scheme for reducing leakage current in an input buffer
US6175248B1 (en) * 1999-05-18 2001-01-16 Level One Communications, Inc. Pulse width distortion correction logic level converter
US6163495A (en) * 1999-09-17 2000-12-19 Cypress Semiconductor Corp. Architecture, method(s) and circuitry for low power memories
US6535735B2 (en) * 2001-03-22 2003-03-18 Skyworks Solutions, Inc. Critical path adaptive power control
US6868503B1 (en) 2002-01-19 2005-03-15 National Semiconductor Corporation Adaptive voltage scaling digital processing component and method of operating the same
JP3730607B2 (ja) * 2002-08-29 2006-01-05 株式会社東芝 差動データドライバー回路
EP1432125B1 (de) * 2002-12-18 2007-08-01 Alcatel Lucent Ein Konverter von ECL nach CMOS für ein digitales Netzwerk
US7446612B2 (en) * 2006-09-08 2008-11-04 Skyworks Solutions, Inc. Amplifier feedback and bias configuration
US7696826B2 (en) * 2006-12-04 2010-04-13 Skyworks Solutions, Inc. Temperature compensation of collector-voltage control RF amplifiers
US7921312B1 (en) 2007-09-14 2011-04-05 National Semiconductor Corporation System and method for providing adaptive voltage scaling with multiple clock domains inside a single voltage domain
US7825693B1 (en) 2009-08-31 2010-11-02 International Business Machines Corporation Reduced duty cycle distortion using controlled body device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4140980A (en) * 1978-02-24 1979-02-20 Rockwell International Corporation Compensation circuit for trailing edge distortion of pulse-width modulated signal
US4524291A (en) * 1983-01-06 1985-06-18 Motorola, Inc. Transition detector circuit
JPS62173692A (ja) * 1986-01-28 1987-07-30 Fujitsu Ltd 半導体集積回路
JPS62230222A (ja) * 1986-03-31 1987-10-08 Toshiba Corp 入力回路
US4868425A (en) * 1987-12-07 1989-09-19 Vtc Incorporated Skew compensated RS422 buffer
DE68917384T2 (de) * 1988-06-24 1995-03-23 Nat Semiconductor Corp Verfahren zum Erhöhen der Geschwindigkeit für CMOS-Schaltungen.
US4958132A (en) * 1989-05-09 1990-09-18 Advanced Micro Devices, Inc. Complementary metal-oxide-semiconductor translator

Also Published As

Publication number Publication date
DE69316680T2 (de) 1998-09-10
TW231385B (en, 2012) 1994-10-01
EP0584946A3 (en) 1995-04-12
KR940005015A (ko) 1994-03-16
DE69316680D1 (de) 1998-03-05
EP0584946A2 (en) 1994-03-02
US5264745A (en) 1993-11-23
EP0584946B1 (en) 1998-01-28

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Effective date: 20001003