JPH0617288Y2 - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPH0617288Y2 JPH0617288Y2 JP1989140899U JP14089989U JPH0617288Y2 JP H0617288 Y2 JPH0617288 Y2 JP H0617288Y2 JP 1989140899 U JP1989140899 U JP 1989140899U JP 14089989 U JP14089989 U JP 14089989U JP H0617288 Y2 JPH0617288 Y2 JP H0617288Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- conductive foil
- semiconductor pellet
- semiconductor
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
ものである。
て、半導体ペレット底面の領域に対応する回路基板上に
形成された導電箔の一部に、導電箔の形成されていない
回路基板の露出部を形成し、半導体ペレットの回路基板
への接着性を良好にし、その信頼性を向上させることの
できる半導体装置を得ようとするものである。
レット3が接着剤5で接着されている。なお、回路基板
1上の半導体ペレット3の取り付け位置に相当する領域
には、導電箔2が形成されている。導電箔2は回路基板
1の一方の電極と導通しており、電磁波等の半導体ペレ
ット3への影響を防止するためのシールドとなっている
ものである。半導体ペレット3のパット10と回路基板
1のボンディングパターン7とはワイヤ8によりワイヤ
ボンディングされて、電気的導通がとれている。この状
態でボンディング等を固定するために、樹脂9で封止さ
れている。
で接着する面は導電箔2の面と半導体ペレットの裏面で
あり、特に、導電箔2の面は平滑であるため、接着力が
弱いものであった。また、回路基板1と半導体ペレット
との間の接着力として影響のする界面は半導体ペレット
3と接着剤5、接着剤5と導電箔2、導電箔2と回路基
板1の3つであるため、接着力に信頼性が小さいもので
あった。
で、半導体ペレットと回路基板との接着力を向上し、且
つその信頼性も向上させることを目的とする。
板に直接半導体ペレットを接着し、半導体ペレットのパ
ットと回路基板のボンディングパターンとをワイヤによ
りワイヤボンディングし、半導体全体を樹脂等で封止す
る、半導体装置において、半導体ペレット底面の領域に
対応する回路基板上に形成されている導電箔に一部円形
の欠損部分を設けて回路基板の露出部分をつくる。以上
の構成により、半導体ペレットの回路基板上への接着力
が向上し、その信頼性もたかくなる。
上に導電箔が形成されていない部分があるため、半導体
ペレットと回路基板とが直接接着剤により、接着されて
いるため接着力が向上するばかりでなく、導電箔が形成
されていない部分の形状が円形であるため、接着剤の流
れが均一になり、導電箔エッジ部の段差に気泡が発生し
にくくなるため、接着力の信頼性も高くなる。
2図はその平面図である。回路基板1上には、半導体3
取り付け位置に対応して、導電箔2が形成されており、
その導電箔2は、その内側が円形上に抜き穴が形成され
ている。つまり、抜き穴部分(露出部)4は導電箔2は
形成されていない。半導体3は接着剤5により、回路基
板1に接着されている。半導体ペレット3のパット10
と回路基板1のボンディングパターン7とはワイヤ8に
てワイヤボンディングされて、電気的導通がとれてい
る。このあと、半導体ペレット3とワイヤボンディング
部との全体を樹脂9にて封止している。回路基板1の半
導体ペレット3の取り付け位置に接着剤5の塗布して、
半導体ペレット3を取り付けると、接着剤5は矢印11
で示すように流れる。接着剤5の流れは半導体ペレット
3を回路基板1に押し当てると、導電箔2の内側エッジ
部20に当たり、導電箔2の上を流れていくが、内側エ
ッジ部20が円形状に形成されているため、その流れは
互いに干渉することがなく均一に流れていく。このた
め、導電箔2の内側エッジ部20に気泡が溜り難くなっ
ている。導電箔の穴抜き部(露出部)は半導体ペレット
3と回路基板1とが直接接着剤5で接着されており、且
つ、導電箔2の穴抜き形状が円形であるため、接着剤に
気泡が溜り難くなっている。
た、導電箔の一部に円形の回路基板の露出部を設けると
言う簡単な構造で接着力が向上し、またその信頼性が高
くなる半導体装置が得られた。なお、導電箔の機能であ
る電磁波等のシールド効果は、従来例のものと殆ど差は
なかった。
は第1図の平面図であり、第3図は、従来例として示し
た半導体装置の断面図である。 1……回路基板 2……導電箔 3……半導体ペレット 4……露出部 5……接着剤 7……ボンディングパターン 8……ワイヤ 9……樹脂 10……パット
Claims (2)
- 【請求項1】導電箔付回路基板に直接半導体ペレットを
接着し、ワイヤボンディングにより前記半導体ペレット
と前記回路基板上のボンディングパターンとを電気的に
接続した後、前記半導体ペレット全体を樹脂により密封
した半導体装置において、 前記半導体ペレット底面の領域に対応する前記回路基板
上の領域に一部前記導電箔を形成しない回路基板露出部
を設けて前記導電箔を形成したことを特徴とする半導体
装置。 - 【請求項2】前記露出部が円形であることを特徴とする
請求項1記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989140899U JPH0617288Y2 (ja) | 1989-12-04 | 1989-12-04 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989140899U JPH0617288Y2 (ja) | 1989-12-04 | 1989-12-04 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0379433U JPH0379433U (ja) | 1991-08-13 |
JPH0617288Y2 true JPH0617288Y2 (ja) | 1994-05-02 |
Family
ID=31687837
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989140899U Expired - Lifetime JPH0617288Y2 (ja) | 1989-12-04 | 1989-12-04 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0617288Y2 (ja) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5810381U (ja) * | 1981-07-15 | 1983-01-22 | 松下電器産業株式会社 | リ−ド線保持具の取付装置 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55173175U (ja) * | 1979-05-29 | 1980-12-12 |
-
1989
- 1989-12-04 JP JP1989140899U patent/JPH0617288Y2/ja not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5810381U (ja) * | 1981-07-15 | 1983-01-22 | 松下電器産業株式会社 | リ−ド線保持具の取付装置 |
Also Published As
Publication number | Publication date |
---|---|
JPH0379433U (ja) | 1991-08-13 |
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