JPH0544829B2 - - Google Patents

Info

Publication number
JPH0544829B2
JPH0544829B2 JP59236483A JP23648384A JPH0544829B2 JP H0544829 B2 JPH0544829 B2 JP H0544829B2 JP 59236483 A JP59236483 A JP 59236483A JP 23648384 A JP23648384 A JP 23648384A JP H0544829 B2 JPH0544829 B2 JP H0544829B2
Authority
JP
Japan
Prior art keywords
chip
wiring
chips
semiconductor
stacked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP59236483A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61113252A (ja
Inventor
Nobuo Sasaki
Motoo Nakano
Junji Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59236483A priority Critical patent/JPS61113252A/ja
Publication of JPS61113252A publication Critical patent/JPS61113252A/ja
Publication of JPH0544829B2 publication Critical patent/JPH0544829B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10W99/00—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10W70/093—
    • H10W70/60—
    • H10W72/07551—
    • H10W72/50—
    • H10W72/853—
    • H10W72/874—
    • H10W72/884—
    • H10W90/00—
    • H10W90/22—
    • H10W90/28—
    • H10W90/732—
    • H10W90/734—
    • H10W90/736—
    • H10W90/754—
    • H10W90/756—

Landscapes

  • Wire Bonding (AREA)
JP59236483A 1984-11-08 1984-11-08 半導体装置 Granted JPS61113252A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59236483A JPS61113252A (ja) 1984-11-08 1984-11-08 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59236483A JPS61113252A (ja) 1984-11-08 1984-11-08 半導体装置

Publications (2)

Publication Number Publication Date
JPS61113252A JPS61113252A (ja) 1986-05-31
JPH0544829B2 true JPH0544829B2 (enExample) 1993-07-07

Family

ID=17001395

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59236483A Granted JPS61113252A (ja) 1984-11-08 1984-11-08 半導体装置

Country Status (1)

Country Link
JP (1) JPS61113252A (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5657206A (en) * 1994-06-23 1997-08-12 Cubic Memory, Inc. Conductive epoxy flip-chip package and method
KR19990061323A (ko) * 1997-12-31 1999-07-26 윤종용 반도체 패키지
US20030006493A1 (en) 2001-07-04 2003-01-09 Matsushita Electric Industrial Co., Ltd. Semiconductor device and manufacturing method thereof
JP4093018B2 (ja) 2002-11-08 2008-05-28 沖電気工業株式会社 半導体装置及びその製造方法
DE102007035902A1 (de) * 2007-07-31 2009-02-05 Siemens Ag Verfahren zum Herstellen eines elektronischen Bausteins und elektronischer Baustein
JP2009194294A (ja) * 2008-02-18 2009-08-27 Toshiba Corp 積層型半導体装置
JP4597182B2 (ja) * 2007-11-09 2010-12-15 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
JP5326449B2 (ja) * 2008-09-10 2013-10-30 コニカミノルタ株式会社 配線形成方法
JP2010232702A (ja) * 2010-07-20 2010-10-14 Toshiba Corp 積層型半導体装置

Also Published As

Publication number Publication date
JPS61113252A (ja) 1986-05-31

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees